CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 54.
xi. lappuse
... University of California , San Diego , USA Rolf Ernst , TU Braunschweig , Germany Daniel Gajski , University of California , Irvine , USA Cathy Gebotys , University of Waterloo , Canada Soonhoi Ha , Seoul National University , Korea ...
... University of California , San Diego , USA Rolf Ernst , TU Braunschweig , Germany Daniel Gajski , University of California , Irvine , USA Cathy Gebotys , University of Waterloo , Canada Soonhoi Ha , Seoul National University , Korea ...
xiii. lappuse
... University of Delft , The Netherlands Tetsuya Aoyama , NEC , Japan Baris Arslan , University of California , San Diego , USA David Atienza , Complutense University of Madrid , Spain Toru Awashima , NEC , Japan Raid Ayoub , University of ...
... University of Delft , The Netherlands Tetsuya Aoyama , NEC , Japan Baris Arslan , University of California , San Diego , USA David Atienza , Complutense University of Madrid , Spain Toru Awashima , NEC , Japan Raid Ayoub , University of ...
xiv. lappuse
... University of Notre Dame , USA Hongchao Liu , University of Notre Dame , USA Zhe Ma , IMEC , Belgium Mateusz Majer , Universität Erlangen - Nürnberg , Germany Mahesh Mamidipaka , University of California , Irvine , USA Pol Marchal ...
... University of Notre Dame , USA Hongchao Liu , University of Notre Dame , USA Zhe Ma , IMEC , Belgium Mateusz Majer , Universität Erlangen - Nürnberg , Germany Mahesh Mamidipaka , University of California , Irvine , USA Pol Marchal ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale