CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 82.
44. lappuse
... table is extracted from the SFG . The designer has defined two different memory mappings in memory table 1 and in memory table 2. Data a , b and c are placed at ad- dress in bank0 . The constant cst is not stored in RAM . Our tool ...
... table is extracted from the SFG . The designer has defined two different memory mappings in memory table 1 and in memory table 2. Data a , b and c are placed at ad- dress in bank0 . The constant cst is not stored in RAM . Our tool ...
196. lappuse
... TABLE An Operation Table ( OT ) is a binding between an op- eration and the processor resources and registers . An OT lists resources that an operation uses in each cycle of its execution . It also contains information about the ...
... TABLE An Operation Table ( OT ) is a binding between an op- eration and the processor resources and registers . An OT lists resources that an operation uses in each cycle of its execution . It also contains information about the ...
225. lappuse
... table look ups ( know as Sbox tables ) are encountered , the key splitting approach requires the tables to be larger and requires an extra table . In the masking countermeasure , each secret piece of data is exclusive - or'd with a ...
... table look ups ( know as Sbox tables ) are encountered , the key splitting approach requires the tables to be larger and requires an extra table . In the masking countermeasure , each secret piece of data is exclusive - or'd with a ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale