CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 11.
51. lappuse
... RTOS The overhead of a software - only RTOS context switch is typically over one thousand cycles , and in the context of MP- SOC's with long NoC latencies , can exceed ten thousand cycles [ 10 ] . The use of hardware engines for message ...
... RTOS The overhead of a software - only RTOS context switch is typically over one thousand cycles , and in the context of MP- SOC's with long NoC latencies , can exceed ten thousand cycles [ 10 ] . The use of hardware engines for message ...
159. lappuse
... RTOS services . To our knowledge , no other cosimulator satisfies all of the above features . This paper is organized as follows . Section 2 surveys related work on hardware / software cosimulation with RTOS supports . Section 3 ...
... RTOS services . To our knowledge , no other cosimulator satisfies all of the above features . This paper is organized as follows . Section 2 surveys related work on hardware / software cosimulation with RTOS supports . Section 3 ...
161. lappuse
... RTOS - specific support tools . 3.4 Timer Unlike the reference simulator of SystemC [ 13 ] or SpecC [ 6 ] , our RTOS - centric cosimulator does not have global timer for managing simulation cycles . Therefore , our cosimulator does not ...
... RTOS - specific support tools . 3.4 Timer Unlike the reference simulator of SystemC [ 13 ] or SpecC [ 6 ] , our RTOS - centric cosimulator does not have global timer for managing simulation cycles . Therefore , our cosimulator does not ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale