CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 80.
19. lappuse
... Figure 2 . sel din inc out sel step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of constraints on ...
... Figure 2 . sel din inc out sel step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of constraints on ...
26. lappuse
... Figure 3 : Dataflow specification of 2 - dimensional DCT algorithm 8 16bit signals 81 - dimensional DCT blocks 8 1 - dimensional DCT blocks DCTID DCTID DCTID DCTID Transpose DCTID Transpose DCTID 64 16bit 8x8 matrix 8x8 matrix DCTID ...
... Figure 3 : Dataflow specification of 2 - dimensional DCT algorithm 8 16bit signals 81 - dimensional DCT blocks 8 1 - dimensional DCT blocks DCTID DCTID DCTID DCTID Transpose DCTID Transpose DCTID 64 16bit 8x8 matrix 8x8 matrix DCTID ...
120. lappuse
... figure 2.a ) . The load and store units are not reconfigured . Using this capability of the Virtex - II devices , we ... figure 9. Figure 9.a. shows the power consumption for a hardware implementation ( with on - chip and off - chip ...
... figure 2.a ) . The load and store units are not reconfigured . Using this capability of the Virtex - II devices , we ... figure 9. Figure 9.a. shows the power consumption for a hardware implementation ( with on - chip and off - chip ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale