CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 66.
54. lappuse
... Computer Engineering Department Carnegie Mellon University Pittsburgh , PA 15213 USA { jpaul , thomas , abobrek}@ece.cmu.edu Figure 7 Airport Scenario Results for Normal e - mail. Abstract Single chip heterogeneous multiprocessors are ...
... Computer Engineering Department Carnegie Mellon University Pittsburgh , PA 15213 USA { jpaul , thomas , abobrek}@ece.cmu.edu Figure 7 Airport Scenario Results for Normal e - mail. Abstract Single chip heterogeneous multiprocessors are ...
55. lappuse
... Computer Architecture ( CA ) , on Right Emphasis is placed on meeting the demands of the I / O stream by direct ... computer embedded in a non - computer system . The need for fixed and guaranteed response times created the real - time ...
... Computer Architecture ( CA ) , on Right Emphasis is placed on meeting the demands of the I / O stream by direct ... computer embedded in a non - computer system . The need for fixed and guaranteed response times created the real - time ...
161. lappuse
... computer , the object code ( i.e. , application tasks and the cosimulator ) is no more than an application process ... computer running on MS - Windows . In Figure 1 , the arrow labeled ( a ) denotes the system call to the host computer ...
... computer , the object code ( i.e. , application tasks and the cosimulator ) is no more than an application process ... computer running on MS - Windows . In Figure 1 , the arrow labeled ( a ) denotes the system call to the host computer ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale