Processor Design: System-On-Chip Computing for ASICs and FPGAsJari Nurmi Springer Science & Business Media, 2007. gada 26. jūl. - 526 lappuses Processor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications. Processor Design provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The types of processor cores covered include general purpose RISC cores, traditional DSP, a VLIW approach to signal processing, processor cores that can be customized for specific applications, reconfigurable processors, protocol processors, Java engines, and stream processors. Co-processor and multi-core design approaches that deliver application-specific performance over and above that which is available from single-core designs are also described. The special design requirements for processors targeted for FPGA implementation, clock generation and distribution in microprocessor circuits, and clockless realization of processors are addressed. Tools and methodologies for application-specific embedded processor design are covered, together with processor modelling and early estimation techniques, and programming tool support for custom processors. The book concludes with a glance to the future of embedded on-chip processors. |
No grāmatas satura
1.–5. rezultāts no 61.
... clock cycle. The number and type of parallel instructions varies from architecture to architecture. issue implementations of the same ISA. Dynamic instruction issue introduces one problem, the possibility for out-of-order execution. To ...
... clock cycle. SMT gets even further by allowing multiple threads to share each execution cycle, i.e., different threads are actually co-executed as opposed to time-multiplexed threads. Thus, in SMT there is physical taneous Multi ...
... clock cycle, a reasonably sized SRAM can be accessed in most cases in a single cycle. Read-Only Memory (ROM) can be used for constant tables or boot-up code, it is very dense with only a single transistor (or none, but the area is the ...
... clock to deliver data. Rambus technology uses a lower voltage swing to deliver data more promptly from the synchronous DRAM. Despite of all the various attempts to speed up dynamic memory, it requires several clock cycles to access data ...
... clock cycles including 282 wait states, compared to fewer than 100 clock cycles for other processors of the era. As a result, Intel's 432 executed common benchmarks 10x to 26x more slowly than a Vax 11/780, and 2x to 23x more slowly ...
Saturs
7 | |
27 | |
Processor Design Flow 69 Capturing requirements | 69 |
GeneralPurpose Embedded Processor Cores The COFFEE | 83 |
The DSP and Its Impact on Technology 101 Introduction | 101 |
Why a DSP is different 105 The evolving architecture of a DSP 113 Summary 119 7 VLIW DSP Processor for HighEnd Mobile Communication | 122 |
8 Customizable Processors and Processor Customization 149 Introduction | 149 |
How microprocessor use differs between | 157 |
Closing comments | 255 |
Hardware abstraction to handle the complexity | 262 |
Java CoProcessor for Embedded Systems 287 Introduction 287 | 309 |
Processor Clock Generation and Distribution 339 Introduction | 339 |
Low power clock distribution 356 Future directions in clock distribution 360 Summary 366 16 Asynchronous and SelfTimed Processor Design 367 ... | 376 |
Summary and conclusions | 388 |
EarlyEstimation Modeling of Processors 391 Introduction 391 History of early estimation models for computer architectures 392 Adapting models to... | 395 |
TACO configurable SystemC simulator 415 Conclusion 425 19 Programming Tools for Reconfigurable Processors 427 Algorithm development on r... | 428 |
Tensilicas extensible Xtensa processor core 162 Conclusion 175 9 RunTime Reconfigurable Processors | 177 |
Coprocessor Approach to Accelerating Multimedia | 209 |
Designing SoftCore Processors for FPGAs 229 Configurable processors | 230 |
the GriffyC approach 439 20 SoftwareBased SelfTesting of Embedded Processors 447 Evolution of softwarebased selftest 452 Highlevel SBST meth... | 476 |
Index | 515 |
Citi izdevumi - Skatīt visu
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2009 |
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2010 |
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2007 |