Processor Design: System-On-Chip Computing for ASICs and FPGAsProcessor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications. Processor Design provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The types of processor cores covered include general purpose RISC cores, traditional DSP, a VLIW approach to signal processing, processor cores that can be customized for specific applications, reconfigurable processors, protocol processors, Java engines, and stream processors. Co-processor and multi-core design approaches that deliver application-specific performance over and above that which is available from single-core designs are also described. The special design requirements for processors targeted for FPGA implementation, clock generation and distribution in microprocessor circuits, and clockless realization of processors are addressed. Tools and methodologies for application-specific embedded processor design are covered, together with processor modelling and early estimation techniques, and programming tool support for custom processors. The book concludes with a glance to the future of embedded on-chip processors. |
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Saturs
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27 | |
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Designing SoftCore Processors for FPGAs | 229 |
Configurable processors | 230 |
Challenges of FPGA processor design | 231 |
Opportunities of FPGA processor design | 232 |
FPGA architecture overview | 234 |
FPGA design issues | 238 |
Instruction set issues | 246 |
FPGA processor instruction set comparison | 249 |
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35 | |
39 | |
Very long instruction word VLIW Medusius Horribilis | 43 |
Overly aggressive pipelining Canalisus Extremus | 45 |
Unbalanced processor design Librius Tiltus | 47 |
Omitting pipeline interlocks Recompilus Requirus | 50 |
Nonpowerof2 dataword widths for generalpurpose computing Datus Unusualus | 53 |
Too small an address space Datus Minimus | 55 |
Memory segmentation Datus Minimus Rex | 58 |
Multithreading Clotho Replicatius | 60 |
Symmetric multiprocessing Multisaur Symmetrius | 63 |
Processor Design Flow | 69 |
Instruction coding | 74 |
Exploration of architecture organizations | 79 |
Hardware and software development | 80 |
Software tools and libraries | 82 |
GeneralPurpose Embedded Processor Cores The COFFEE RISC Example | 83 |
Implications of RISC design philosophy | 84 |
The COFFEE RISC Core instruction set architecture | 86 |
Software view of the COFFEE RISC Core | 88 |
Hardware view of the COFFEE RISC Core | 90 |
The COFFEE RISC Core pipeline structure | 92 |
The COFFEE RISC Core implementation | 95 |
The COFFEE RISC Core characteristics | 97 |
Conclusions | 100 |
The DSP and Its Impact on Technology | 101 |
Why a DSP is different | 105 |
The evolving architecture of a DSP | 113 |
What is next in the evolution of the DSP | 115 |
Summary | 119 |
VLIW DSP Processor for HighEnd Mobile Communication Applications | 120 |
Trends in mobile communication | 122 |
DSPspecific requirements | 124 |
Microarchitectural concepts | 126 |
VLIW and SW programmability | 128 |
3a an application specific adaptable core architecture | 130 |
kernel versus application benchmarking | 139 |
Design space exploration | 142 |
The complexity of configurability | 145 |
Summary | 147 |
Acknowledgment | 148 |
Customizable Processors and Processor Customization | 149 |
A benefits analysis of processor customization | 150 |
Using microprocessor cores in SOC design | 153 |
Benefiting from microprocessor extensibility | 154 |
How microprocessor use differs between SOC and boardlevel design | 157 |
Tensilicas extensible Xtensa processor core | 162 |
The TIE language | 169 |
Conclusion | 175 |
RunTime Reconfigurable Processors | 177 |
Embedded microprocessor trends | 178 |
Instruction set metamorphosis | 180 |
Reconfigurable computing | 184 |
Runtime reconfigurable instruction set processors | 186 |
Coarsegrained reconfigurable processors | 196 |
Conclusions | 205 |
Coprocessor Approach to Accelerating Multimedia Applications | 209 |
Accelerators and different types of parallelism | 210 |
Processor architectures and different approaches to acceleration | 211 |
Requirements of applications for hardware coprocessors | 212 |
floatingpoint units | 214 |
Various types of reconfigurable accelerators | 215 |
Milk coprocessor and Butter accelerator | 217 |
Conclusions | 226 |
Case study Nios II | 250 |
Closing comments | 255 |
Acknowledgments | 256 |
Protocol Processor Design Issues | 257 |
Domain and application analysis for optimized protocol processing hardware | 259 |
Hardware abstraction to handle the complexity of specifications | 262 |
Custom design frameworks | 264 |
Design processes | 266 |
The TACO framework for protocol processor design | 268 |
Conclusions | 284 |
Java CoProcessor for Embedded Systems | 286 |
Generic virtual machine architecture | 288 |
Using hardware systems in virtual machine implementations | 290 |
Structure of the coprocessor | 291 |
Current status and future work | 307 |
Summary | 308 |
Stream Multicore Processors | 309 |
Raw architecture overview | 315 |
Related architectures | 319 |
Raw chip implementation | 322 |
Methodology for performance analysis | 324 |
Stream computation | 328 |
ILP computation | 333 |
Bitlevel computation | 335 |
Conclusion | 337 |
Acknowledgments | 338 |
Processor Clock Generation and Distribution | 339 |
Clock parameters and trends | 340 |
Clock distribution networks | 344 |
Deskew circuits | 350 |
Jitter reduction techniques | 354 |
Low power clock distribution | 356 |
Future directions in clock distribution | 360 |
Summary | 366 |
Asynchronous and SelfTimed Processor Design | 367 |
The development of asynchronous processors | 370 |
Asynchronous design styles | 373 |
Features of asynchronous design | 376 |
Summary and conclusions | 388 |
EarlyEstimation Modeling of Processors | 391 |
History of early estimation models for computer architectures | 392 |
Adapting models to meet modern processor architectures | 394 |
Architecture modeling | 395 |
Processor logic optimization at 90 nm technology | 400 |
Physical design issues in the era of sub100 nm technologies | 403 |
System Level Simulations | 405 |
Simulation and languages | 411 |
TACO configurable SystemC simulator | 415 |
Highlevel instruction set simulator generator for COFFEE Risc Core | 422 |
Conclusion | 425 |
Programming Tools for Reconfigurable Processors | 427 |
Algorithm development on reconfigurable processors programming issues | 428 |
Instruction set extension implementation on a standard compilation toolchain | 430 |
Bridging the gap from hardware to software through Cdescribed dataflow graphs | 434 |
Overview of programming tools for reconfigurable processors | 437 |
the GriffyC approach | 439 |
SoftwareBased SelfTesting of Embedded Processors | 447 |
Evolution of softwarebased selftest | 452 |
Highlevel SBST methodology | 463 |
Case studies experimental results | 476 |
Conclusions and perspective | 481 |
Future Directions in Processor Design | 482 |
References | 487 |
Index | 515 |
Citi izdevumi - Skatīt visu
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2009 |
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2010 |
Processor Design: System-On-Chip Computing for ASICs and FPGAs Jari Nurmi Priekšskatījums nav pieejams - 2007 |