The Designer's Guide to VHDLThe Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from the system level to the gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. The book is organized so that it can be either read cover-to-cover for a comprehensive tutorial or kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. All of the examples and case studies, complete with test drivers for running the VHDL code, are available via the World Wide Web. In addition, each chapter is followed by a set of related exercises. |
No grāmatas satura
1.3. rezultāts no 58.
242. lappuse
1 Aliases for Data Objects If we have a model that includes a data object , such
as a constant , a variable , a signal or , as we see in a later chapter , a file , we
can declare an alias for the object with an alias declaration . A simplified syntax
rule ...
1 Aliases for Data Objects If we have a model that includes a data object , such
as a constant , a variable , a signal or , as we see in a later chapter , a file , we
can declare an alias for the object with an alias declaration . A simplified syntax
rule ...
473. lappuse
The two variables point to the same data object . then the value we get via count2
. all is 20 . Note that when we copied the pointer from count1 to count2 , we
overwrote the pointer to the data object 10 . The object itself is still stored in
memory ...
The two variables point to the same data object . then the value we get via count2
. all is 20 . Note that when we copied the pointer from count1 to count2 , we
overwrote the pointer to the data object 10 . The object itself is still stored in
memory ...
475. lappuse
On the other hand , we can create an access type that points to data objects of an
unconstrained array type , for example ... We can create an array object using an
allocator that includes a qualified aggregate , for example : activation _ times ...
On the other hand , we can create an access type that points to data objects of an
unconstrained array type , for example ... We can create an array object using an
allocator that includes a qualified aggregate , for example : activation _ times ...
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actual allows architecture body array associated attribute begin behavioral bit_vector block boolean called cell changes Chapter character clock complete component instance condition configuration connected constant contains conversion counter cycle defined delay described determine Develop downto driver element end process entity entity declaration example executed expression false function identifier implementation indication initial input instantiation instruction integer interface label logic loop memory module natural Note object operand operations output package parameter perform port map position procedure range record refer represent reset resolved result shown in Figure shows signal signal assignment simulation specify statement std_logic stored string structure subtype syntax rule tion token transaction unit variable vector VHDL wait write
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Bibliogrāfiskā informācija
| Nosaukums | The Designer's Guide to VHDL |
| Autors | Peter J. Ashenden |
| Izdevums: | 2 |
| Izdevējs | Morgan Kaufmann, 1996 |
| Oriģināls no | Mičiganas universitāte |
| Digitalizēta | 13.12.2007 |
| ISBN | 1558602704, 9781558602700 |
| Apjoms | 688 lappuses |
| Eksportēt avotu | BiBTeX EndNote RefMan |