The Designer's Guide to VHDLThe Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from the system level to the gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. The book is organized so that it can be either read cover-to-cover for a comprehensive tutorial or kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. All of the examples and case studies, complete with test drivers for running the VHDL code, are available via the World Wide Web. In addition, each chapter is followed by a set of related exercises. |
No grāmatas satura
1.3. rezultāts no 83.
256. lappuse
FIGURE 10 - 4 function bv _ to _ natural ( bv : in bit _ vector ) return natural is
variable result : natural : = 0 ; begin for index in by ' range loop result : = result * 2
+ bit ' pos ( bv ( index ) ) ; end loop ; return result ; end function bv _ to _ natural ...
FIGURE 10 - 4 function bv _ to _ natural ( bv : in bit _ vector ) return natural is
variable result : natural : = 0 ; begin for index in by ' range loop result : = result * 2
+ bit ' pos ( bv ( index ) ) ; end loop ; return result ; end function bv _ to _ natural ...
470. lappuse
Values of type natural _ ptr can only point to natural numbers , not to objects of
any other type . In general , we can write access type declarations referring to any
VHDL type except file types . Once we have declared an access type , we can ...
Values of type natural _ ptr can only point to natural numbers , not to objects of
any other type . In general , we can write access type declarations referring to any
VHDL type except file types . Once we have declared an access type , we can ...
596. lappuse
EXAMPLE Suppose a library contains the following entity , which generates a
random number at regular intervals : entity random _ source is generic ( min ,
max : natural ; seed : natural ; interval : delay _ length ) ; port ( number : out
natural ) ...
EXAMPLE Suppose a library contains the following entity , which generates a
random number at regular intervals : entity random _ source is generic ( min ,
max : natural ; seed : natural ; interval : delay _ length ) ; port ( number : out
natural ) ...
Lietotāju komentāri - Rakstīt atsauksmi
Ierastajās vietās neesam atraduši nevienu atsauksmi.
Saturs
Fundamental Concepts | 1 |
Exercises | 25 |
Exercises | 51 |
Autortiesības | |
26 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
actual allows architecture body array associated attribute begin behavioral bit_vector block boolean called cell changes Chapter character clock complete component instance condition configuration connected constant contains conversion counter cycle defined delay described determine Develop downto driver element end process entity entity declaration example executed expression false function identifier implementation indication initial input instantiation instruction integer interface label logic loop memory module natural Note object operand operations output package parameter perform port map position procedure range record refer represent reset resolved result shown in Figure shows signal assignment simulation specify statement std_logic stored string structure subtype syntax rule tion token transaction true unit variable vector VHDL wait write
Atsauces uz šo grāmatu
Turings Connectionism: An Investigation of Neural Network Architectures Christof Teuscher Ierobežota priekšskatīšana - 2002 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bibliogrāfiskā informācija
| Nosaukums | The Designer's Guide to VHDL |
| Autors | Peter J. Ashenden |
| Izdevums: | 2 |
| Izdevējs | Morgan Kaufmann, 1996 |
| Oriģināls no | Mičiganas universitāte |
| Digitalizēta | 13.12.2007 |
| ISBN | 1558602704, 9781558602700 |
| Apjoms | 688 lappuses |
| Eksportēt avotu | BiBTeX EndNote RefMan |