The Designer's Guide to VHDLThe Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from the system level to the gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. The book is organized so that it can be either read cover-to-cover for a comprehensive tutorial or kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. All of the examples and case studies, complete with test drivers for running the VHDL code, are available via the World Wide Web. In addition, each chapter is followed by a set of related exercises. |
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1.3. rezultāts no 56.
66. lappuse
We can do this by labeling the outer loop and using the label in the exit statement
. We can write loop _ name : loop exit loop _ name ; end loop loop _ name ; This
labels the loop with the name loop _ name , so that we can indicate which loop ...
We can do this by labeling the outer loop and using the label in the exit statement
. We can write loop _ name : loop exit loop _ name ; end loop loop _ name ; This
labels the loop with the name loop _ name , so that we can indicate which loop ...
67. lappuse
next statement [ label : ) next [ loop _ label ] [ when boolean _ expression ) ; The
optional label at the start of the next statement serves to identify the statement .
We discuss labeled statements in Chapter 20 . A next statement is very similar in
...
next statement [ label : ) next [ loop _ label ] [ when boolean _ expression ) ; The
optional label at the start of the next statement serves to identify the statement .
We discuss labeled statements in Chapter 20 . A next statement is very similar in
...
647. lappuse
if statemente Lif _ label : ) if boolean _ expression then { sequential _ statement }
{ elsif boolean _ expression then { sequential _ statement } } [ else { sequential
statement } ] end if Lif _ label ] ; case _ statement = ( case _ label : 1 case ...
if statemente Lif _ label : ) if boolean _ expression then { sequential _ statement }
{ elsif boolean _ expression then { sequential _ statement } } [ else { sequential
statement } ] end if Lif _ label ] ; case _ statement = ( case _ label : 1 case ...
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actual allows architecture body array associated attribute begin behavioral bit_vector block boolean called cell changes Chapter character clock complete component instance condition configuration connected constant contains conversion counter cycle defined delay described determine Develop downto driver element end process entity entity declaration example executed expression false function identifier implementation indication initial input instantiation instruction integer interface label logic loop memory module natural Note object operand operations output package parameter perform port map position procedure range record refer represent reset resolved result shown in Figure shows signal signal assignment simulation specify statement std_logic stored string structure subtype syntax rule tion token transaction unit variable vector VHDL wait write
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Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bibliogrāfiskā informācija
| Nosaukums | The Designer's Guide to VHDL |
| Autors | Peter J. Ashenden |
| Izdevums: | 2 |
| Izdevējs | Morgan Kaufmann, 1996 |
| Oriģināls no | Mičiganas universitāte |
| Digitalizēta | 13.12.2007 |
| ISBN | 1558602704, 9781558602700 |
| Apjoms | 688 lappuses |
| Eksportēt avotu | BiBTeX EndNote RefMan |