The Designer's Guide to VHDL
Elsevier Science & Technology Books, 1996 - 688 lappuses
The Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from the system level to the gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. The book is organized so that it can be either read cover-to-cover for a comprehensive tutorial or kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. All of the examples and case studies, complete with test drivers for running the VHDL code, are available via the World Wide Web. In addition, each chapter is followed by a set of related exercises.
Scalar Data Types and Operations
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actual alias allows architecture body array assertion association attribute begin behavioral bit_vector block boolean called changes Chapter character clause clock complete component condition configuration connected constant contains convert defined delay described determine Develop downto driver element end process entity entity declaration example executed expression false function identifier implementation indicates initial input instance instantiation instruction integer interface label literal logic loop memory mode module multiplication natural Note object operand operation output package parameter perform port map position procedure produce range record refer represent reset resolved result selected shown in Figure shows signal assignment simulation specify statement std_logic stored string structure subtype syntax rule tion token transaction unit variable vector VHDL wait write
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