Solid-State Circuits, vol. SC-22, pp. 899—901, October 1987. [2] J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, pp. 62—70, February 1989. Low-Power Electronics Design - 9-2. lappuselaboja - 2018 - 912 lapasIerobežota priekšskatīšana - Par šo grāmatu
| Magdy Bayoumi, Earl Swartzlander - 1994 - 258 lapas
...Chains”, lEE Electronics Letters, vol. 28, No. 14, pp. 1334- 1335, 1992. [60] Yuan, J., Svennson, C. “High-Speed CMOS Circuit Technique.” IEEE. J. Solid-State Circuits. vol. 24 pp. 62-70, 1989. [61] Afghahi, M., Svensson, C. “A Unified Single-Phase Clocking Scheme for VLSI Systems.”... | |
| Gary K. Yeap, Farid N. Najm - 1996 - 136 lapas
...split-level charge recovery logic", Proc. of Int. Workshop on Low Power Design, Apr. 1994, pp. 177-182. 47. J. Yuan and C. Svensson, "High-speed CMOS circuit technique", IEEE J. Solid-State Circuits 24 (1989) 62-70. LOW POWER DESIGN OF OFF-CHIP DRIVERS AND TRANSMISSION LINES: A BRANCH AND BOUND APPROACH... | |
| Michael Shur - 1996 - 388 lapas
...CMOS technique for pipelined logic structures", IEEE J. Solid State Cir. 18 (1983) 261-266. 59. J.-R. Yuan and C. Svensson, "High-speed CMOS circuit technique", IEEE J. SolidState Circuits 24, 1 (1989) 62-70. 60. F. Lu et al., "A 700 MHz 24-6 pipelined accumulator in 1.2 fiia CMOS for application... | |
| |