Low-Power Electronics DesignChristian Piguet CRC Press, 2018. gada 3. okt. - 912 lappuses The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. |
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1.–5. rezultāts no 83.
... operation, the direct-tunneling current remains high for a gate oxide thickness of about 2 or 2.5 nm [2]. Every 0.2-nm reduction between 2 and 1 nm implies an increase of an order of magnitude of gate-tunneling current. For devices with ...
... operation requires an island size of less than about 1 nm, the size of a small molecule. In addition, we also require that the source and drain be weakly coupled to the gated island, which is usually accomplished by introducing tunnel ...
... operation within the circuit and with other circuits, and reduced immunity to temperature variations. Important constraints when developing the optical interconnect layer are the fact that all fabrication steps have to be compatible ...
... operation, and single-mode operation (i.e., only one mode is allowed in the gain spectrum). From the viewpoint of mode field confinement and mirror reflection, two types of microcavity structures exist: multiple reflection (VCSELs and ...
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Saturs
2-1 | |
3-1 | |
4-1 | |
5-1 | |
Section II LowPower Circuits | 5-21 |
Chapter 6 Modeling for Designing in Deep Submicron Technologies | 6-1 |
Chapter 7 Logic Circuits and Standard Cells | 7-1 |
Chapter 8 LowPower Very Fast Dynamic Logic Circuits | 8-1 |
Section IV LowPower Systems on Chips | 26-13 |
Chapter 27 Power Performance TradeOffs in Design of SoCs | 27-1 |
Chapter 28 LowPower SoC with PowerAware Operating Systems Generation | 28-1 |
Chapter 29 LowPower Data Storage and Communication for SoC | 29-1 |
EnergyEfficient Design of SoC Interconnect | 30-1 |
Chapter 31 Highly Integrated UltraLow Power RF Transceivers for Wireless Sensor Networks | 31-1 |
Chapter 32 PowerAware OnDemand Routing Protocols for Mobile Ad Hoc Networks | 32-1 |
Chapter 33 Modeling Computational Sensing and Actuation Surfaces | 33-1 |
Chapter 9 LowPower Arithmetic Operators | 9-1 |
Chapter 10 Circuits Techniques for Dynamic Power Reduction | 10-1 |
Chapter 11 VHDL for Low Power | 11-1 |
Chapter 12 Clocking MultiGHz Systems | 12-1 |
Chapter 13 Circuit Techniques for Leakage Reduction | 13-1 |
Chapter 14 LowPower and LowVoltage Communication for SoCs | 14-1 |
Chapter 15 Adiabatic and ClockPowered Circuits | 15-1 |
Chapter 16 Weak Inversion for Ultimate LowPower Logic | 16-1 |
Chapter 17 Robustness of Digital Circuits at Lower Voltages | 17-1 |
Section III LowPower Processors and Memories | 17-25 |
Chapter 18 Techniques for Power and Process Variation Minimization | 18-1 |
Chapter 19 LowPower DSPs | 19-1 |
Chapter 20 EnergyEfficient Reconfigurable Processors | 20-1 |
Chapter 21 Macgic a LowPower Reconfigurable DSP | 21-1 |
Chapter 22 LowPower Asynchronous Processors | 22-1 |
Chapter 23 LowPower Baseband Processors for Communications | 23-1 |
Chapter 24 StandBy Power Reduction for SRAM Memories | 24-1 |
Chapter 25 LowPower Cache Design | 25-1 |
Chapter 26 Memory Organization for LowEnergy Embedded Systems | 26-1 |
Section V Embedded Software | 33-15 |
Chapter 34 LowPower Software Techniques | 34-1 |
Chapter 35 LowPowerEnergy Compiler Optimizations | 35-1 |
Chapter 36 Design of LowPower Processor Cores Using a Retargetable Tool Flow | 36-1 |
Chapter 37 Recent Advances in LowPower Design and Functional Coverification Automation from the Earliest SystemLevel Design Stages | 37-1 |
Section VI CAD Tools for Low Power | 37-25 |
Chapter 38 HighLevel Power Estimation and Analysis | 38-1 |
Chapter 39 Power MacroModels for HighLevel Power Estimation | 39-1 |
Chapter 40 Synopsys LowPower Design Flow | 40-1 |
Chapter 41 Magma LowPower Flow | 41-1 |
Chapter 42 Sequence Design Flow for PowerSensitive Design | 42-1 |
Section VII Battery Cells Sources of Energy and Chip Cooling | 42-19 |
Chapter 43 Battery Lifetime Optimization for EnergyAware Circuits | 43-1 |
Chapter 44 Miniature Fuel Cells for Portable Applications | 44-1 |
Chapter 45 HumanGenerated Power for Mobile Electronics | 45-1 |
Why 8211 How | 46-1 |
Back cover | I-23 |
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