Low-Power Electronics Design

Pirmais vāks
Christian Piguet
CRC Press, 2018. gada 3. okt. - 912 lappuses

The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design.

This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management.

The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now.

No grāmatas satura

Atlasītās lappuses

Saturs

Chapter 2 Evolution of Deep Submicron Bulk and SOI Technologies
2-1
Chapter 3 Leakage in CMOS Nanometric Technologies
3-1
Chapter 4 Microelectronics Nanoelectronics and the Future of Electronics
4-1
Chapter 5 Advanced Research in OnChip Optical Interconnects
5-1
Section II LowPower Circuits
5-21
Chapter 6 Modeling for Designing in Deep Submicron Technologies
6-1
Chapter 7 Logic Circuits and Standard Cells
7-1
Chapter 8 LowPower Very Fast Dynamic Logic Circuits
8-1
Section IV LowPower Systems on Chips
26-13
Chapter 27 Power Performance TradeOffs in Design of SoCs
27-1
Chapter 28 LowPower SoC with PowerAware Operating Systems Generation
28-1
Chapter 29 LowPower Data Storage and Communication for SoC
29-1
EnergyEfficient Design of SoC Interconnect
30-1
Chapter 31 Highly Integrated UltraLow Power RF Transceivers for Wireless Sensor Networks
31-1
Chapter 32 PowerAware OnDemand Routing Protocols for Mobile Ad Hoc Networks
32-1
Chapter 33 Modeling Computational Sensing and Actuation Surfaces
33-1

Chapter 9 LowPower Arithmetic Operators
9-1
Chapter 10 Circuits Techniques for Dynamic Power Reduction
10-1
Chapter 11 VHDL for Low Power
11-1
Chapter 12 Clocking MultiGHz Systems
12-1
Chapter 13 Circuit Techniques for Leakage Reduction
13-1
Chapter 14 LowPower and LowVoltage Communication for SoCs
14-1
Chapter 15 Adiabatic and ClockPowered Circuits
15-1
Chapter 16 Weak Inversion for Ultimate LowPower Logic
16-1
Chapter 17 Robustness of Digital Circuits at Lower Voltages
17-1
Section III LowPower Processors and Memories
17-25
Chapter 18 Techniques for Power and Process Variation Minimization
18-1
Chapter 19 LowPower DSPs
19-1
Chapter 20 EnergyEfficient Reconfigurable Processors
20-1
Chapter 21 Macgic a LowPower Reconfigurable DSP
21-1
Chapter 22 LowPower Asynchronous Processors
22-1
Chapter 23 LowPower Baseband Processors for Communications
23-1
Chapter 24 StandBy Power Reduction for SRAM Memories
24-1
Chapter 25 LowPower Cache Design
25-1
Chapter 26 Memory Organization for LowEnergy Embedded Systems
26-1
Section V Embedded Software
33-15
Chapter 34 LowPower Software Techniques
34-1
Chapter 35 LowPowerEnergy Compiler Optimizations
35-1
Chapter 36 Design of LowPower Processor Cores Using a Retargetable Tool Flow
36-1
Chapter 37 Recent Advances in LowPower Design and Functional Coverification Automation from the Earliest SystemLevel Design Stages
37-1
Section VI CAD Tools for Low Power
37-25
Chapter 38 HighLevel Power Estimation and Analysis
38-1
Chapter 39 Power MacroModels for HighLevel Power Estimation
39-1
Chapter 40 Synopsys LowPower Design Flow
40-1
Chapter 41 Magma LowPower Flow
41-1
Chapter 42 Sequence Design Flow for PowerSensitive Design
42-1
Section VII Battery Cells Sources of Energy and Chip Cooling
42-19
Chapter 43 Battery Lifetime Optimization for EnergyAware Circuits
43-1
Chapter 44 Miniature Fuel Cells for Portable Applications
44-1
Chapter 45 HumanGenerated Power for Mobile Electronics
45-1
Why 8211 How
46-1
Back cover
I-23
Autortiesības

Citi izdevumi - Skatīt visu

Bieži izmantoti vārdi un frāzes

Populāri fragmenti

3-1. lappuse - a novel semiconductor device with a subthreshold slope lower than kT/q, IEDM Tech. Dig., pp. 289—292, 2002. [8] T. Kuroda et al. “Variable threshold-voltage CMOS technology, IEICE Trans. Electron., Vol. E83-C, No. 11, November 2000. [9] A. Keshavarzi et al. Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's,
17-2. lappuse - Ion-implanted complementary MOS transistors in low-voltage circuits, IEEE J. Solid-State Circuits, vol. SC-7, April 1972, pp. 146—153. [2] H. Soeleman and K. Roy, Ultra-low power digital subthreshold logic circuits, Proc. Int. Symp. on Low-Power Electronics and Design, pp. 94—96, 1999. [3] J. Burr and J. Shott, A 200-mV self-testing encoder/decoder using Stanford ultra-low-power CMOS,
5-21. lappuse - 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration, Proc. IEEE, 89, 602, 2001. [5] Miller, DAB Rationale and challenges for optical interconnects to electronic chips, Proc. IEEE, 88, 728, 2000. [6] Davis,
13-18. lappuse - Circuits, 35, 1009, 2000. [17] Sirisantana, N., Wei, L., and Roy, K., High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness, Proc. 2000 Int. Conf on Computer Design, 227, Sept.
10-8. lappuse - that the output multiplexer can be controlled at f/2. The operation or access of a Unit 2 is started before the completion of the operation of Unit 1. Therefore, M successive computations do not have to be dependent on each other.
10-7. lappuse - (10.4) At first order, power could be saved even if V¿, is not reduced; however, some overhead has to be considered, such as the address registers duplication and the output multiplexer (Figure 10.3). If this overhead is not too expensive, such a parallelization scheme has to be considered for logic modules that are not on the critical path. At a low V,,¿,
10-7. lappuse - is reduced. As operating frequency is reduced, however, the use of cells with smaller or unsized transistors results in a power reduction. Furthermore, some parallelized logic modules do not require M-unit duplication. It is the case, for instance, for memories [25], in which each unit contains 1/M data or instructions, resulting in the same total area to store the information and in the same
9-2. lappuse - Solid-State Circuits, vol. SC-22, pp. 899—901, October 1987. [2] J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, pp. 62—70, February 1989.
13-2. lappuse - [13] IE Sutherland, Micropipelines, Commun. ACM, Vol. 32, No. 6, June 1989. [14] A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Oberg, P. Ellervee, and D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchronous design style, Proc. 36th Design Automation Conf, June 21—25, 1999. [15] VG
8-2. lappuse - 02, Monterey, CA, August 12—14, 2002, pp. 108—111. [4] S. Nikolaidis and A. Chatzigeorgiou, Circuit-level low-power design, Chapter 4 in Designing CMOS Circuits for Low-Power, D. Soudris, C. Piguet, and C. Goutis, Eds., Kluwer Academic Press, Dordrecht, 2002. [5] LG Heller et al. Cascode voltage switch logic: a differential CMOS logic family, Proc.

Atsauces uz šo grāmatu

Par autoru (2018)

Christian Piguet

Bibliogrāfiskā informācija