Low-Power Electronics DesignChristian Piguet CRC Press, 2018. gada 3. okt. - 912 lappuses The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. |
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1.5. rezultāts no 69.
... efficiency of the active devices is of prime importance in this context. In addition, particular attention has to be paid to the receiver: the signal to noise ratio determines the minimal optical power at the detector. Efficient ...
... efficiency (including optical coupling), and acceptable transmission losses. Power can then be estimated from source bias current and photoreceiver front-end design methodologies. For integration density aspects, source and detector ...
... efficiency from waveguide to optical receiver. In the proposed system, the coupling efficiency LCR from the waveguide to the optical receiver is assumed to be 87% [18]. 5.3.2. Resonators. Microdisks are resonating structures and are most ...
... efficiency of some 40%. Threshold currents are typically in the mA range. It is clear that effort is required from the research community if VCSELs are to compete in the on-chip optical interconnect arena, to increase wavelength, efficiency ...
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Saturs
2-1 | |
3-1 | |
4-1 | |
5-1 | |
Section II LowPower Circuits | 5-21 |
Chapter 6 Modeling for Designing in Deep Submicron Technologies | 6-1 |
Chapter 7 Logic Circuits and Standard Cells | 7-1 |
Chapter 8 LowPower Very Fast Dynamic Logic Circuits | 8-1 |
Section IV LowPower Systems on Chips | 26-13 |
Chapter 27 Power Performance TradeOffs in Design of SoCs | 27-1 |
Chapter 28 LowPower SoC with PowerAware Operating Systems Generation | 28-1 |
Chapter 29 LowPower Data Storage and Communication for SoC | 29-1 |
EnergyEfficient Design of SoC Interconnect | 30-1 |
Chapter 31 Highly Integrated UltraLow Power RF Transceivers for Wireless Sensor Networks | 31-1 |
Chapter 32 PowerAware OnDemand Routing Protocols for Mobile Ad Hoc Networks | 32-1 |
Chapter 33 Modeling Computational Sensing and Actuation Surfaces | 33-1 |
Chapter 9 LowPower Arithmetic Operators | 9-1 |
Chapter 10 Circuits Techniques for Dynamic Power Reduction | 10-1 |
Chapter 11 VHDL for Low Power | 11-1 |
Chapter 12 Clocking MultiGHz Systems | 12-1 |
Chapter 13 Circuit Techniques for Leakage Reduction | 13-1 |
Chapter 14 LowPower and LowVoltage Communication for SoCs | 14-1 |
Chapter 15 Adiabatic and ClockPowered Circuits | 15-1 |
Chapter 16 Weak Inversion for Ultimate LowPower Logic | 16-1 |
Chapter 17 Robustness of Digital Circuits at Lower Voltages | 17-1 |
Section III LowPower Processors and Memories | 17-25 |
Chapter 18 Techniques for Power and Process Variation Minimization | 18-1 |
Chapter 19 LowPower DSPs | 19-1 |
Chapter 20 EnergyEfficient Reconfigurable Processors | 20-1 |
Chapter 21 Macgic a LowPower Reconfigurable DSP | 21-1 |
Chapter 22 LowPower Asynchronous Processors | 22-1 |
Chapter 23 LowPower Baseband Processors for Communications | 23-1 |
Chapter 24 StandBy Power Reduction for SRAM Memories | 24-1 |
Chapter 25 LowPower Cache Design | 25-1 |
Chapter 26 Memory Organization for LowEnergy Embedded Systems | 26-1 |
Section V Embedded Software | 33-15 |
Chapter 34 LowPower Software Techniques | 34-1 |
Chapter 35 LowPowerEnergy Compiler Optimizations | 35-1 |
Chapter 36 Design of LowPower Processor Cores Using a Retargetable Tool Flow | 36-1 |
Chapter 37 Recent Advances in LowPower Design and Functional Coverification Automation from the Earliest SystemLevel Design Stages | 37-1 |
Section VI CAD Tools for Low Power | 37-25 |
Chapter 38 HighLevel Power Estimation and Analysis | 38-1 |
Chapter 39 Power MacroModels for HighLevel Power Estimation | 39-1 |
Chapter 40 Synopsys LowPower Design Flow | 40-1 |
Chapter 41 Magma LowPower Flow | 41-1 |
Chapter 42 Sequence Design Flow for PowerSensitive Design | 42-1 |
Section VII Battery Cells Sources of Energy and Chip Cooling | 42-19 |
Chapter 43 Battery Lifetime Optimization for EnergyAware Circuits | 43-1 |
Chapter 44 Miniature Fuel Cells for Portable Applications | 44-1 |
Chapter 45 HumanGenerated Power for Mobile Electronics | 45-1 |
Why 8211 How | 46-1 |
Back cover | I-23 |
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