Assertion-Based DesignSpringer Science & Business Media, 2004. gada 19. maijs - 390 lappuses Chapter 3 Specifying RTL Properties 61 3. 1 Definitions and concepts 62 62 3. 1. 1 Property 3. 1. 2 Events 65 3. 2 Property classification 65 Safety versus liveness 66 3. 2. 1 3. 2. 2 Constraint versus assertion 67 3. 2. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 3. 1 3. 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3. 3 3. 3. 4 PSL and default clock declaration 74 3. 3. 5 Specifying sequences 75 3. 3. 6 Specifying eventualities 80 3. 3. 7 PSL built-in functions 82 3. 4Pragma-based assertions 82 3. 5 SystemVerilog assertions 84 3. 5. 1 Immediate assertions 84 3. 5. 2Concurrent assertions 86 3. 5. 3 System functions 95 3. 6 PCI property specification example 96 3. 6. 1 PCI overview 96 3. 7 Summary 102 Chapter 4 PLI-Based Assertions 103 4. 1 Procedural assertions 104 4. 1. 1 A simple PLI assertion 105 4. 1. 2 Assertions within a simulation time slot 108 4. 1. 3 Assertions across simulation time slots 111 4. 1. 4 False firing across multiple time slots 116 4. 2 PLI-based assertion library 118 4. 2. 1 Assert quiescent state 119 4. 3 Summary 123 Chapter 5 Functional Coverage 125 5. 1 Verification approaches 126 5. 2 Understanding coverage 127 5. 2. 1 Controllability versus observability 128 5. 2. |
Saturs
Introduction | 3 |
Assertion Methodology | 23 |
Specifying RTL Properties | 63 |
PLIBased Assertions | 105 |
Functional Coverage | 127 |
Assertion Patterns | 163 |
Assertion Cookbook | 213 |
Specifying Correct Behavior | 269 |
Open Verification Library | 293 |
PSL Property Specification Language | 319 |
SystemVerilog Assertions | 351 |
Bibliography | 375 |
Index | 381 |
Citi izdevumi - Skatīt visu
Assertion-Based Design Harry D. Foster,Adam C. Krolnik,David J. Lacey Ierobežota priekšskatīšana - 2006 |
Assertion-Based Design Harry D. Foster,Adam C. Krolnik,David J. Lacey Ierobežota priekšskatīšana - 2012 |
Assertion-Based Design Harry D. Foster,Adam C. Krolnik,David J. Lacey Ierobežota priekšskatīšana - 2004 |
Bieži izmantoti vārdi un frāzes
Accellera adding assertions assert_always assert_never assertion methodology assertion monitor assertion patterns behavior bits block Boolean expression bugs cache line code coverage complete condition cycle Cyrix debug default clock defined demonstrates described detected disable iff enable encoding ensure evaluates event FIFO FL_Property flush formal verification functional coverage model functional coverage points hardware verification languages Hence high-level identify implication operator input instantiated interface invalidate logic match module multiple multiplexer occur one-hot opcode options output parameter Pattern name phase pipeline PLI-based assertion posedge clk Problem procedural assertions Property Specification Language property_expr protocol provides PSL property queue repetition request requirements reset_n routine rst_n RTL code RTL implementation sequence sequence_expr SERE severity_level shown in Example signal simulation specify functional coverage start_event Syntax SystemVerilog temporal test_expr testbench transaction valid variable verification environment Verilog VHDL write
Atsauces uz šo grāmatu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |