VHDL Designer’s ReferenceSpringer Science & Business Media, 1992. gada 31. maijs - 455 lappuses too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • Which modeling methodology should be adopted? • How should the VHDL environment be customized? • What are the tricks? Where are the traps? • What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company. |
Saturs
VHDL TOOLS | 13 |
22 EVALUATING VHDL TOOLS | 14 |
23 TECHNOLOGY OF PLATFORMS | 24 |
VHDL AND MODELING ISSUES | 37 |
32 CORE VHDL CONCEPTS | 38 |
33 ABSTRACTION | 58 |
34 HIERARCHY | 60 |
36 REUSABILITY | 64 |
84 OBJECTS AND TYPES | 200 |
85 PREDEFINED OPERATORS AND FUNCTIONS | 204 |
86 STATEMENTS | 208 |
87 DESCRIPTION LEVEL | 211 |
88 TRANSLATING FROM M TO VHDL | 216 |
89 CONCLUSION | 221 |
VERILOG AND VHDL | 223 |
92 DESIGN UNIT | 224 |
37 PORTABILITY | 71 |
39 DOCUMENTATION | 73 |
310 SYNTHESIS | 76 |
311 CONCLUSION | 89 |
STRUCTURING THE ENVIRONMENT | 91 |
42 UTILITY PACKAGES AND LIBRARIES | 105 |
SYSTEM MODELING | 121 |
PETRINETS | 126 |
STATE CHARTS AND SNETS | 134 |
55 CONCLUSION | 137 |
STRUCTURING METHODOLOGY | 139 |
62 WHAT ARE THE POSSIBILITIES OF VHDL? | 140 |
63 TO SUMMARIZE | 153 |
TRICKS AND TRAPS | 157 |
72 MODELING TRICKS | 174 |
73 PITFALLS | 184 |
74 DESIGNER COMMANDMENTS | 186 |
M AND VHDL | 189 |
82 DESIGN UNIT | 190 |
83 SEQUENTIAL AND CONCURRENT DOMAINS | 197 |
93 SEQUENTIAL AND CONCURRENT DOMAINS | 229 |
94 OBJECTS AND TYPES | 235 |
95 PREDEFINED OPERATORS FUNCTIONS AND GATES | 243 |
96 STATEMENTS | 248 |
97 DESCRIPTION LEVEL | 271 |
98 TRANSLATING FROM VERILOG TO VHDL | 277 |
99 CONCLUSION | 308 |
UDLI AND VHDL | 311 |
102 DESIGN UNIT | 312 |
103 SEQUENTIAL AND CONCURRENT DOMAINS | 319 |
104 OBJECTS AND TYPES | 322 |
105 UDLI STRUCTURAL DESCRIPTION | 334 |
106 UDLI BEHAVIORAL DESCRIPTION | 340 |
107 UDLI ASSERTION SECTION | 366 |
108 DESCRIPTION LEVEL | 369 |
109 TRANSLATING FROM UDLI TO VHDL | 373 |
1010 CONCLUSION | 382 |
MEMO | 385 |
INDEX | 441 |
Citi izdevumi - Skatīt visu
VHDL Designer’s Reference Jean-Michel Bergé,Alain Fonkoua,Serge Maginot,Jacques Rouillard Ierobežota priekšskatīšana - 2012 |
VHDL Designer's Reference Jean-Michel Berge,Alain Fonkoua,Serge Maginot Priekšskatījums nav pieejams - 2014 |
VHDL Designer’s Reference Jean-Michel Bergé,Alain Fonkoua,Serge Maginot,Jacques Rouillard Priekšskatījums nav pieejams - 2012 |
Bieži izmantoti vārdi un frāzes
architecture ARC array automaton begin end behavior bit arrays BIT VECTOR clause clock compiled Concurrent Domains concurrent statements CONF of ENT configuration CONF continuous assignment dataflow datatypes defined delay design entity design units don't-care downto driver driving value elsif end block end component end loop end PCK end process end record ENT is architecture ENT is package entity declaration entity ENT enumeration type equivalent example executed expression hardware description language implementation inout input instantiation INTEGER integrated circuits LATCH logic synthesis logic type logic value module multi-value logic nand netlist operators package declaration parameter port map predefined procedural assignment process begin process statement reference manual RESET resolution function return UDLI_BIT semantics sequential statements signal assignment statement simulation specification STATE1 subprograms subtype synchronous type BIT UDL/I UDLI UDLI_BIT_VECTOR user-defined variable Verilog primitive VHDL model VHDL process wait statement waveform XBIT