ESL Design and Verification: A Prescription for Electronic System Level MethodologyElsevier, 2010. gada 27. jūl. - 488 lappuses Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors!Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.Table of ContentsCHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts |
No grāmatas satura
1.–5. rezultāts no 88.
vii. lappuse
... Verification Environment Provision . . . . . . . . . . . . 99 4.4.3 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.4 Verification Simulation . . . . . . . Contents vii.
... Verification Environment Provision . . . . . . . . . . . . 99 4.4.3 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.4 Verification Simulation . . . . . . . Contents vii.
xii. lappuse
... Verification Planning Automation . . . . . . . . . . . . 314 10.3 Verification Environment Implementation . . . . . . . . . . . . . 316 10.3.1 Write Verification Environment . . . . . . . . . . . . . 316 10.4 Verification Results ...
... Verification Planning Automation . . . . . . . . . . . . 314 10.3 Verification Environment Implementation . . . . . . . . . . . . . 316 10.3.1 Write Verification Environment . . . . . . . . . . . . . 316 10.4 Verification Results ...
8. lappuse
... environment for ESL software, are discussed in detail, along with relevant approaches for debugging system software using models and tools. □ Chapter 13, Use of ESL for Implementation Verification, discusses how the design flow from ...
... environment for ESL software, are discussed in detail, along with relevant approaches for debugging system software using models and tools. □ Chapter 13, Use of ESL for Implementation Verification, discusses how the design flow from ...
29. lappuse
... verification environment A verification environment—sometimes known as a testbench—capable of achieving 100% coverage without any external input, such as tests. See section 10.2.2.1, “Stimulus Generation.” Behavioral A model of a system ...
... verification environment A verification environment—sometimes known as a testbench—capable of achieving 100% coverage without any external input, such as tests. See section 10.2.2.1, “Stimulus Generation.” Behavioral A model of a system ...
30. lappuse
... (verification environment) to verify the correctness of the design. Electronic system level The use of appropriate abstractions to increase comprehension of a system and enhance the probability of successfully implementing its ...
... (verification environment) to verify the correctness of the design. Electronic system level The use of appropriate abstractions to increase comprehension of a system and enhance the probability of successfully implementing its ...
Saturs
1 | |
11 | |
35 | |
Chapter 4 WHAT ARE THE ENABLERS OF ESL? | 81 |
Chapter 5 ESL FLOW | 113 |
Chapter 6 SPECIFICATIONS AND MODELING | 139 |
Chapter 7 PREPARTITIONING ANALYSIS | 175 |
Chapter 8 PARTITIONING | 205 |
Chapter 10 POSTPARTITIONING VERIFICATION | 295 |
Chapter 11 HARDWARE IMPLEMENTATION | 333 |
Chapter 12 SOFTWARE IMPLEMENTATION | 379 |
Chapter 13 USE OF ESL FOR IMPLEMENTATION VERIFICATION | 399 |
Chapter 14 RESEARCH EMERGING AND FUTURE PROSPECTS | 425 |
LIST OF ACRONYMS | 447 |
Index | 451 |
Chapter 9 POSTPARTITIONING ANALYSIS AND DEBUG | 265 |
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ESL Design and Verification: A Prescription for Electronic System Level ... Brian Bailey,Grant Martin,Andrew Piziali Priekšskatījums nav pieejams - 2007 |
Bieži izmantoti vārdi un frāzes
abstraction levels algorithm application approach architecture aspects behavioral synthesis blocks Chapter chip clock code coverage communication companies compiler complex components computation concurrency configurable constraints coprocessor cost coverage model cycle dataptr DCT_SIZE debug defined design flow design space discussed domain dynamic embedded systems engineers ESL design ESL flow ESL models example executable specification F/OSS FIFO Figure FPGA functional functional verification hardware hardware and software hardware design high-level HW/SW IEEE input interface JTAG language latency level of abstraction logic mapping memory methodology metrics multiple operating optimization OSCI partitioning performance platform possible post-partitioning pre-partitioning analysis problem processor protocol real-time requirements reuse scheduling silicon simulation software development standard static STMicroelectronics synthesis tool system design system-level SystemC SystemVerilog taxonomy techniques Tensilica tion Transaction-Level Modeling verification environment verification plan Verilog VHDL VLIW Xilinx
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