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...sufficient accuracy. References 1. Gupta, S., Najm, FN: Power Modeling for High-Level Power Estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 1, (2000) 18—29 2. Theoharis, S., Theodoridis, G., Soudris, D., Goutis, C.: Accurate Data Path Models... | |
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...Bogliolo and G. De Micheli "A Survey of Design Techniques for System-Level Dynamic Power Management," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, June 2000. [2] I. Hong, G. Qu, M. Potkonjak and MB Srivastava, "Synthesis techniques for low-power... | |
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...and C. Hawkins, "Intrinsic Leakage in Deep Submicron CMOS ICs - Measurement-Based Test Solutions," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 6, pp. 717-723, 2000. [12] A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis, "Design Considerations... | |
 | Jari Nurmi - 2004 - 474 lapas
...Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp. 195-206, April 2000. [15] K. Banerjee and A. Mehrotra, "Analysis of On-Chip Inductance Effects... | |
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...Codes, Amsterdam, The Netherlands: North-Holland, 1996. [136] H. Zhang,V George and JM Rabaey,"Low swing on-chip signaling techniques: Effectiveness and robustness,"...Transactions on Very Large Scale Integration (VLSI) Systems,Vol. 8, No. 3, August 2000, pp. 264-272. [137] R. Hegde and NR Shanbhag, "Toward achieving... | |
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