Networks on Chips: Technology and Tools
Elsevier, 2006. gada 30. aug. - 408 lappuses
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution.
This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
* Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends
* An integrated presentation not currently available in any other book
* A thorough introduction to current design methodologies and chips designed with NoCs
Lietotāju komentāri - Rakstīt atsauksmi
Ierastajās vietās neesam atraduši nevienu atsauksmi.
7 NoC Programming
8 Design Methodologies and CAD Tool Flows for NoCs
9 Designs and Implementations of NoCBased SoCs
Citi izdevumi - Skatīt visu
algorithms AMBA application arbitration Automation and Test bandwidth bits block buffer busses cache capacitance channel circuit switching circuits clock codeword communication protocol complex Computer configuration connection crossbar crosstalk cycles cyclic code deadlock decoding delay destination dynamic efficient encoding end-to-end energy error detection FIGURE flit flow control FPGA frequency global guaranteed Hamming code hardware header IEEE IEEE Transactions implementation input latency layer logic master mesh mesochronous modules MPSoC multiple network interface Networks on Chip NoC architecture NoC design nodes noise on-chip networks operation optimization output packet packet switching parallel parameters path payload performance pipelined platform port power consumption programming protocol queue router routing schemes shared memory signal simulation slave specific switching synchronization SystemC T-Error techniques Test in Europe tion topology traffic virtual channels virtual circuits VLSI wires xpipes
13. lappuse - Hence, communication-energy minimization will be a growing concern in future technologies. Furthermore, network traffic control and monitoring can help in better managing the power consumed by networked computational resources. For instance, clock speed and voltage of end nodes can be varied according to available network bandwidth.
ii. lappuse - Silicon presents high-quality, peer-reviewed books authored by leading experts in the field who are uniquely qualified to address these issues. The Designer's Guide to VHDL, Second Edition Peter J. Ashenden The System Designer's Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson and Darrell A. Teegarden...
16. lappuse - The main purpose of data-link protocols is to increase the reliability of the link up to a minimum required level, under the assumption that the physical layer by itself is not sufficiently reliable. An additional source of errors is contention in shared-medium networks. Contention resolution is fundamentally a non-deterministic process because it requires synchronization of a distributed system, and for this reason it can be seen as an additional noise source.
200. lappuse - A survey of wormhole routing techniques in direct networks,
16. lappuse - Contention resolution is fundamentally a non-deterministic process because it requires synchronization of a distributed system, and for this reason it can be seen as an additional noise source. In general, non-determinism can be virtually eliminated at the price of some performance penalty. For instance, centralized bus arbitration in a synchronous bus eliminates contentioninduced errors, at the price of a substantial performance penalty caused by the slow bus clock and by bus request/release cycles....
73. lappuse - Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE Journal Of Solid-State Circuits, vol.
143. lappuse - Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp.
16. lappuse - At the data link layer, error correction can be achieved by using standard error correcting codes (ECC) that add redundancy to the transferred information. Error correction can be complemented by several packet-based error detection and recovery protocols. Several parameters in these protocols (eg, packet size, number of outstanding packets, etc.) can be adjusted depending on the goal to achieve maximum performance at a specified residual error probability and/or within given energy consumption bounds....
16. lappuse - At the network layer, packetized data transmission can be customized by the choice of switching and routing algorithms. The former establishes the type of connection while the latter determines the path followed by a message through the network to its final destination.
74. lappuse - An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSI's,