VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, FranceGiovanni De Micheli, Salvador Mir, Ricardo Reis Springer, 2010. gada 23. aug. - 394 lappuses This book contains extended and revised versions of the best papers that were presented during the fourteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 14th conference was held at the Hotel Boscolo, Nice, France (October 16-18, 2006). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt and Perth. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI- SOC conferences aim to address these exciting new issues. |
No grāmatas satura
1.–5. rezultāts no 19.
18. lappuse
... threshold voltage Vth . The integrator is reset when the comparator output flips creating the folded waveform shown in Fig. 15(b). Meanwhile, the integrator output is sampled and digitized at predefined sampling or capture times t1 ,t2 ...
... threshold voltage Vth . The integrator is reset when the comparator output flips creating the folded waveform shown in Fig. 15(b). Meanwhile, the integrator output is sampled and digitized at predefined sampling or capture times t1 ,t2 ...
47. lappuse
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
48. lappuse
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
49. lappuse
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
50. lappuse
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Saturs
24 | |
Electronic Detection of DNA Adsorption and Hybridization | 54 |
Shekhar Borkar | 69 |
A Survey of Probabilistic CMOS Technology | 101 |
Time | 119 |
Soft Error Resilient System Design through Error Correction 143 | 142 |
Library Compatible Variational Delay Computation | 157 |
A PowerEfficient Methodology for Mapping Applications on Multi | 177 |
Configurable OnLine Global Energy Optimization in MultiCore | 217 |
Logic Synthesis of EXOR Projected Sum of Products | 241 |
Optimization 281 | 280 |
Broadside Transition Test Generation for Partial Scan Circuits | 301 |
Comparison of an Æthereal Network on Chip and Traditional | 317 |
Designing Routing and MessageDependent Deadlock Free | 337 |
Dynamic Reconfigurable Architecture Exploration based | 357 |
Emerging Technology for Body Area Networks Julien Penders Bert Gyselinckx Ruud Vullers Olivier Rousseaux | 377 |
Citi izdevumi - Skatīt visu
VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth ... Giovanni De Micheli,Salvador Mir,Ricardo Reis Priekšskatījums nav pieejams - 2007 |
VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth ... Giovanni De Micheli,Salvador Mir,Ricardo Reis Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
achieve algorithm analysis application approach architecture array buffer cell chip circuit clock combinational communication compared components computation Conference configuration connections considered constraints consumption core correction corresponding cycles delay depends detection device distribution dynamic effective electronic energy error estimated example execution fault Figure flow frequency function gain gate given IEEE impact implementation increase input integration interconnect International limited logic mapping measurement memory method minimal needed node Note obtained operation optimal output parameters partitioning path performance possible presented probabilistic probability problem processor proposed range reconfigurable reduced reference respectively sample scaling schedule sensor shown shows signal simulation soft error solution specific speed step switch Table task technique tion transistors transition types variability variations voltage
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