VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France
This book contains extended and revised versions of the best papers that were presented during the fourteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 14th conference was held at the Hotel Boscolo, Nice, France (October 16-18, 2006). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt and Perth. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI- SOC conferences aim to address these exciting new issues.
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Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices
Electronic Detection of DNA Adsorption and Hybridization
Probabilistic Statistical Design the Wave of the Future
A CMOS MixedMode SampleandHold Circuit for Pipelined ADCs
A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design
TimeDependent Variability and its Impact on Embedded System Design
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots
Conﬁgurable OnLine Global Energy Optimization in MultiCore Embedded Systems Using Principles of Analog Computation
Logic Synthesis of EXOR Projected Sum of Products
A Method for IO Pins Partitioning Targeting 3D VLSI Circuits
CAT Platform for Analogue and MixedSignal Test Evaluation and Optimization
Broadside Transition Test Generation for Partial Scan Circuits through Stuckat Test Generation
Comparison of the Æthereal Network on Chip and Traditional Interconnects Two Case Studies
Designing Routing and MessageDependent Deadlock Free Networks on Chips
Soft Error Resilient System Design through Error Correction
Library Compatible Variational Delay Computation
A PowerEfficient Methodology for Mapping Applications on MultiProcessor SystemOnChip Architectures
Exploration based on Parameterized Reconfigurable Processor Model
Emerging Technology for Body Area Networks
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VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth ...
Giovanni De Micheli,Salvador Mir,Ricardo Reis
Priekšskatījums nav pieejams - 2007
3D-Vias algorithm analysis application array bandwidth buffer capacitance cell clock CMOS components computation Config configuration connections considered constraints core deadlocks delay detection device dynamic voltage scaling electronic embedded systems energy consumption EP-SOP execution cycles fault coverage frequency function genetic algorithm hardware I/O pins IEEE impact implementation increase input integration interconnect Latch latency logic mapping memory message types method netlist Networks on Chips node op amp operation optimal output overhead parameters partial scan circuits path PCMOS performance power consumption probabilistic problem Proc processor proposed reconfigurable architecture reduced robot router S/H circuit sample schedule sensor shown in Figure signal simulation soft error soft error rate solution SOP form speed SRAM stuck-at supply voltage switch Systems on Chip target TDMA technique test metrics threshold voltage tiers tion topology transistors variability variations VLSI WCEC
ii. lappuse - IFIP's aim is two-fold: to support information processing within its member countries and to encourage technology transfer to developing nations. As its mission statement clearly states, IF IP's mission is to be the leading, truly international, apolitical organization which encourages and assists in the development, exploitation and application of information technology for the benefit of all people. IFIP is a non-profitmaking organization, run almost solely by 2500 volunteers.
ii. lappuse - IFIP's events range from an international congress to local seminars, but the most important are: the IFIP World Computer Congress, held every second year; open conferences; working conferences. The flagship event is the IFIP World Computer Congress, at which both invited and contributed papers are presented. Contributed papers are rigorously refereed and the rejection rate is high. As with the Congress, participation in the open conferences is open to all and papers may be invited or...
101. lappuse - School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia 30332-0250 Abstract This paper considers hardware support for the exploitation of control parallelism on data parallel architectures.
176. lappuse - J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates,
155. lappuse - Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Transactions on Nuclear Science, vol.
176. lappuse - The generalized adjoint network and network sensitivities," IEEE Trans, on Circuit Theory, vol.
179. lappuse - Dynamic power management  is a design methodology that dynamically adapts an embedded system to provide the requested services and performance levels with a minimum number of active components. This methodology is based on the idea that not all system components are always required to be in the active state, and peak performance is only required during some time intervals.
196. lappuse - R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times.