VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France

Pirmais vāks
Giovanni De Micheli, Salvador Mir, Ricardo Reis
Springer, 2010. gada 23. aug. - 394 lappuses
This book contains extended and revised versions of the best papers that were presented during the fourteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 14th conference was held at the Hotel Boscolo, Nice, France (October 16-18, 2006). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt and Perth. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI- SOC conferences aim to address these exciting new issues.

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Architectures for High Dynamic Range High Speed Image Sensor Readout Circuits
Oversampled Time Estimation Techniques for Precision Photonic Detectors
Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices
Electronic Detection of DNA Adsorption and Hybridization
Probabilistic Statistical Design the Wave of the Future
A CMOS MixedMode SampleandHold Circuit for Pipelined ADCs
A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design
TimeDependent Variability and its Impact on Embedded System Design
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots
Configurable OnLine Global Energy Optimization in MultiCore Embedded Systems Using Principles of Analog Computation
Logic Synthesis of EXOR Projected Sum of Products
A Method for IO Pins Partitioning Targeting 3D VLSI Circuits
CAT Platform for Analogue and MixedSignal Test Evaluation and Optimization
Broadside Transition Test Generation for Partial Scan Circuits through Stuckat Test Generation
Comparison of the Æthereal Network on Chip and Traditional Interconnects Two Case Studies
Designing Routing and MessageDependent Deadlock Free Networks on Chips

Soft Error Resilient System Design through Error Correction
Library Compatible Variational Delay Computation
A PowerEfficient Methodology for Mapping Applications on MultiProcessor SystemOnChip Architectures
Exploration based on Parameterized Reconfigurable Processor Model
Emerging Technology for Body Area Networks

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