Readings in Computer Architecture

Pirmais vāks
Gulf Professional Publishing, 2000 - 717 lappuses

Thanks to the continued exponential advances in semiconductor design and the demands of evolving and emerging application domains, the field of computer architecture has never been more dynamic. This, the first major book of computer architecture readings in over two decades, captures this dynamism and reveals Computer Architecture's rich history of practice.

This is much more than a simple collection of papers. The editors have carefully selected the most influential primary sources in specific areas of inquiry that, taken together, present the critical issues of the entire discipline. These include issues in technology, implementation, economics, evaluation methods, instruction set design, instruction level parallelism, dataflow/multithreading, memory systems, input/output systems, single-instruction multiple data parallelism, and multiple-instruction multiple data parallelism. In addition, you'll find the editors' thoughtful, focused introductions to each area, providing the context and background necessary for understanding the significance and lasting impact of these papers.

The primary sources and insightful commentary contained in this book provide foundational knowledge for computer architects as well as for those who design supporting system software and compilers. This is an excellent resource for practitioners, instructors, students, and researchers.

Features

* Includes more than 50 influential papers spanning four decades of computer architecture research and development

* Selected, edited, and introduced by three eminent researchers and educators in the field.

* Demonstrates the value of primary sources by showing how forgotten design ideas of the past are often rediscovered when new needs or constraints emerge.

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Saturs

Architecture of the IBM System360
17
Parallel Operation in the Control Data 6600
32
CRAY1 Computer Technology
50
Methods
69
Evaluating Associativity in CPU Caches
82
A Characterization of Processor Performance in the VAX11780
101
Compilers and Computer Architecture
119
Minicomputer
126
LockupFree Instruction FetchPrefetch Cache Organization
380
Improving DirectMapped Cache Performance by the Addition of
395
Simulation and Measurement
418
Organization and Performance of a TwoLevel Virtual Real Cache Hierarchy
434
A SequencingBased Taxonomy of IO Systems and Review of Historical Machines
451
A Case for Redundant Arrays of Inexpensive Disks RAID
474
A Survey of Wormhole Routing Techniques in Direct Networks
492
Reality Engine Graphics
507

Computers Complexity and Controversy
144
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
163
Machine Philosophy and InstructionHandling
185
Implementing Precise Interrupts in Piplined Processors
202
TwoLevel Adaptive Training Branch Prediction
228
Instruction Issue Logic for HighPerformance Interruptable Pipelined Processors
244
The Mips R10000 Superscalar Microprocessor
275
History Overview and Perspective
288
Dataflow and Multithreading
309
Executing a Program on the MIT TaggedToken Dataflow Architecture
323
Architecture and Applications of the HEP Multiprocessor Computer System
342
Memory Systems
363
The Burroughs Scientific Processor BSP
528
The Terasys Massively Parallel PIM Array
542
Reflections in a Pool of ProcessorsAn Experience Report on C mmpHydra
561
How to Make a Multiprocessor Computer that Correctly Executes
574
DDMA CacheOnly Memory Architecture
600
Memory Coherence in Shared Virtual Memory Systems
623
Recent Implementations and Future Prospects
643
Tuning the Pentium Pro Microarchitecture
660
The Microprocessor Today
668
The Future of Microprocessors
681
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Par autoru (2000)

Mark D. Hill is Professor and Romnes Fellow in the Computer Sciences and Electrical and Computer Engineering departments at the University of Wisconsin-Madison. His research targets the memory systems of shared-memory multiprocessors and high-performance uniprocessors. Much of his recent work was part of the Wisconsin Wind Tunnel project, which examined supporting multiple parallel programming models on hardware ranging from tightly-coupled multiprocessors to clusters of workstations.

Norman P. Jouppi is Consulting Engineer at Compaq Computer Corporation's Western Research Laboratory (WRL). Formerly a consulting associate professor in the Department of Electrical Engineering at Stanford University, he has been a key contributor to the architecture and implementation of advanced graphics accelerators (including Neon), the MultiTitan and BIPS microprocessors at WRL, and the MIPS Stanford microprocessor.

Gurindar S. Sohi, a Professor in the Computer Sciences and Electrical and Computer Engineering departments of the University of Wisconsin-Madison, was awarded the 1999 ACM SIGARCH Maurice Wilkes award for contributions in the areas of high issue rate processors and instruction level parallelism. His research has focused on architectural and microarchitectural techniques for high-performance microprocessors.

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