 | Reiner W. Hartenstein, Andres Keevallik - 1998 - 808 lapas
...SRAM designs. In to appear in Proc. of Great Lakes Symposium on VLSI, 2000. 32. K. Inoue, T.Ishthara, and K. Murakami. Way-predicting set-associative cache...for high performance and low energy consumption. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 273-275, 1999.... | |
 | Thambipillai Srikanthan, Jingling Xue - 2005 - 850 lapas
...Hasegawa et al. "SH3: High Code Density, Low Power". IEEE Micro, 15(6):11-19, December 1995. 11. K. Inoue, T. Ishihara, and K. Murakami. "Way-Predicting...for High Performance and Low Energy Consumption". Proc. Int. Symp. on Low Power Electronics and Design, pp 273-275, Aug. 1999. 12. MB Kamble and K. Ghose.... | |
 | Jiannong Cao - 2005 - 539 lapas
...International Symposium on Microarchitecture (MICRO-33) (2000) 214-220 11. Inoue, K. Ishihara. T. Murakami, K.: Way-predicting Set-associative Cache for High Performance and Low Energy Consumption, in Proc. Int. Low Power Electronics and Design Symp. (1999)273-275 12. Chang, YJ Lai, F. Kuan. SJ: An Efficient... | |
 | Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer - 2007 - 307 lapas
...benchmark suite. In Proc. IEEE 4th Workshop on Workload Characterization, pages 3-14, Dec. 2001. 12. K. Inoue, T. Ishihara, and K. Murakami. Way-predicting...high performance and low energy consumption. In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design, pages 273—275, Aug. 1999. 13.... | |
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K. Inoue, T. Ishihara, and K. Murakami. Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption. 