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" S. Heo, K. Barr, M. Hampton, and K. Asanovic. Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines. "
Computer Architecture Techniques for Power-efficiency - 196. lappuse
autors: Stefanos Kaxiras, Margaret Martonosi - 2008 - 207 lapas
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Multiprocessor Systems-on-Chips

Ahmed Jerraya, Wayne Wolf - 2005 - 604 lapas
...Silicon Research Center Annual Review, 2002. [34] Heo, S., Barr, K., Hampton, M., and Asanovic, K. Dynamic fine-grain leakage reduction using leakage-biased...Annual International Symposium on Computer Architecture (ISCA-29), pp. 137-147, 2002. [35] Koyama, T, Inoue, K., Hanaki, H., Yasue, M., and Iwata, E. A 250-MHz...
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Systems Self-Assembly: Multidisciplinary Snapshots

2011 - 304 lapas
...Kim, JE Smith, An instruction set and microarchitecture for instruction level distributed processing, in: Proceedings of the 29th Annual International Symposium on Computer Architecture, May 2002. [16] TH LaBean, H. Yan, J. Kopatsch, F. Liu, E. Winfree, JH Reif, N. Seeman, Construction, analysis,...
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