Computer Architecture Techniques for Power-efficiencyMorgan & Claypool Publishers, 2008 - 207 lappuses In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. |
No grāmatas satura
1.5. rezultāts no 63.
vi. lappuse
... significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. KEYWORDS Computer power consumption, computer energy consumption ...
... significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. KEYWORDS Computer power consumption, computer energy consumption ...
viii. lappuse
... Significance Compression 62 4.3.3 Further Reading on Narrow Width Operands 64 4.4 Idle - Width Switching Activity : Caches 64 4.4.1 Dynamic Zero Compression : Accessing Only Significant Bits . . . . . . .65 4.4.2 Value Compression and ...
... Significance Compression 62 4.3.3 Further Reading on Narrow Width Operands 64 4.4 Idle - Width Switching Activity : Caches 64 4.4.1 Dynamic Zero Compression : Accessing Only Significant Bits . . . . . . .65 4.4.2 Value Compression and ...
2. lappuse
... significant leakage paths yet.) During the transition period of the 1980s, many viewed CMOS as too slow for widespread use in the high-performance microprocessor arena. Though researchers in semiconductor device technologies explored ...
... significant leakage paths yet.) During the transition period of the 1980s, many viewed CMOS as too slow for widespread use in the high-performance microprocessor arena. Though researchers in semiconductor device technologies explored ...
9. lappuse
... significant importance. For data centers and other utility computing scenarios, energy consumption ranks as one of the leading operating costs and thus reducing energy usage is crucial [71, 203] Power: Power is the rate of energy ...
... significant importance. For data centers and other utility computing scenarios, energy consumption ranks as one of the leading operating costs and thus reducing energy usage is crucial [71, 203] Power: Power is the rate of energy ...
10. lappuse
... significant relevance even in energy- or power-constrained environments. With the dual goals of low energy and fast runtimes in mind, energy-delay product (EDP) was proposed as a useful metric [85]. EDP offers equal weight to either ...
... significant relevance even in energy- or power-constrained environments. With the dual goals of low energy and fast runtimes in mind, energy-delay product (EDP) was proposed as a useful metric [85]. EDP offers equal weight to either ...
Saturs
1 | |
9 | |
23 | |
Optimizing Capacitance and Switching Activity to Reduce Dynamic Power | 45 |
Managing Static Leakage Power | 131 |
Conclusions | 181 |
Citi izdevumi - Skatīt visu
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Ierobežota priekšskatīšana - 2008 |
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Ierobežota priekšskatīšana - 2022 |
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Priekšskatījums nav pieejams - 2008 |
Bieži izmantoti vārdi un frāzes
adaptive approach architectural techniques behavior bit-line segmentation bits Bloom filters branch prediction buffer byte cache decay cache line CAM-tag capacitance chip circuit clock gating clock-gated CMOS compression Computer Architecture configuration core counters cycles decay interval decay-induced misses direct-mapped disabled domino logic drowsy mode DVFS dynamic power dynamic voltage scaling Electronics and Design encoding execution factor Figure frequency frequent value functional units global hardware idle IEEE implementation increase inputs instruction cache instruction queue issue latches latency leakage power logic loop Low Power Electronics low-power M. J. Irwin memoization Microarchitecture microprocessor misprediction miss rate narrow-width operands operation optimizations partition performance phase pipeline power consumption power dissipation prediction Proc processor proposed resizing reuse scaling Section set-associative cache significant slack SRAM structures subthreshold leakage superscalar supply voltage switching activity Symp TAG DATA TAG thermal threshold voltage transistor width wire wordlines
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