Computer Architecture Techniques for Power-efficiencyMorgan & Claypool Publishers, 2008 - 207 lappuses In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. |
No grāmatas satura
1.–5. rezultāts no 40.
ix. lappuse
... Prediction 4.9.4 Advanced Way - Prediction Mechanisms 4.9.5 Way Selection .... 4.9.6 Coherence Protocols .. 4.10 Cacheable Switching Activity 4.10.1 Work Reuse .. 4.10.2 Filter Cache 4.10.3 Loop Cache 4.10.4 Trace Cache .. 4.11 ...
... Prediction 4.9.4 Advanced Way - Prediction Mechanisms 4.9.5 Way Selection .... 4.9.6 Coherence Protocols .. 4.10 Cacheable Switching Activity 4.10.1 Work Reuse .. 4.10.2 Filter Cache 4.10.3 Loop Cache 4.10.4 Trace Cache .. 4.11 ...
5. lappuse
... predicted clocks in excess of 6 GHz by roughly 2006. Power consumption is also one important factor driving the adoption of chip multiprocessors (CMPs) since they allow high-throughput computing to be performed within cost-effective ...
... predicted clocks in excess of 6 GHz by roughly 2006. Power consumption is also one important factor driving the adoption of chip multiprocessors (CMPs) since they allow high-throughput computing to be performed within cost-effective ...
12. lappuse
... predictions across technology generations (and therefore spanning values of V and f ) are attempted. At a high level ... predicting the behavior of one possible chip design by appropriately scaling per- module power behaviors observed ...
... predictions across technology generations (and therefore spanning values of V and f ) are attempted. At a high level ... predicting the behavior of one possible chip design by appropriately scaling per- module power behaviors observed ...
27. lappuse
... predict the future. As with the previous algorithms, its interval size can be adjusted for different results. PAST works under the assumption that the next interval is similar to the current one. Although this may seem naive, PAST ...
... predict the future. As with the previous algorithms, its interval size can be adjusted for different results. PAST works under the assumption that the next interval is similar to the current one. Although this may seem naive, PAST ...
34. lappuse
... predict future power behavior based on recently observed values [ 116 ] . This so - called Global Phase History Table ( GPHT ) is inspired by hardware branch predictors , but is implemented in software by the operating system . Like a ...
... predict future power behavior based on recently observed values [ 116 ] . This so - called Global Phase History Table ( GPHT ) is inspired by hardware branch predictors , but is implemented in software by the operating system . Like a ...
Saturs
1 | |
9 | |
23 | |
Optimizing Capacitance and Switching Activity to Reduce Dynamic Power | 45 |
Managing Static Leakage Power | 131 |
Conclusions | 181 |
Citi izdevumi - Skatīt visu
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Ierobežota priekšskatīšana - 2008 |
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Ierobežota priekšskatīšana - 2022 |
Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras,Margaret Martonosi Priekšskatījums nav pieejams - 2008 |
Bieži izmantoti vārdi un frāzes
adaptive approach architectural techniques behavior bit-line segmentation bits Bloom filters branch prediction buffer byte cache decay cache line CAM-tag capacitance chip circuit clock gating clock-gated CMOS compression Computer Architecture configuration core counters cycles decay interval decay-induced misses direct-mapped disabled domino logic drowsy mode DVFS dynamic power dynamic voltage scaling Electronics and Design encoding execution factor Figure frequency frequent value functional units global hardware idle IEEE implementation increase inputs instruction cache instruction queue issue latches latency leakage power logic loop Low Power Electronics low-power M. J. Irwin memoization Microarchitecture microprocessor misprediction miss rate narrow-width operands operation optimizations partition performance phase pipeline power consumption power dissipation prediction Proc processor proposed resizing reuse scaling Section set-associative cache significant slack SRAM structures subthreshold leakage superscalar supply voltage switching activity Symp TAG DATA TAG thermal threshold voltage transistor width wire wordlines
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