Computer Architecture Techniques for Power-efficiency

Pirmais vāks
Morgan & Claypool Publishers, 2008 - 207 lappuses
In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics.

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Saturs

Introduction
1
Modeling Simulationand Measurement
9
Using Voltage and Frequency Adjustments to ManageDynamic Power
23
Optimizing Capacitance and Switching Activity to Reduce Dynamic Power
45
Managing Static Leakage Power
131
Conclusions
181
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Populāri fragmenti

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196. lappuse - Hsu and U. Kremer. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction.
194. lappuse - In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 40-46, October 1999.
197. lappuse - K. Inoue, T. Ishihara, and K. Murakami. Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption.
191. lappuse - L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, "Address bus encoding techniques for system-level power optimization,
191. lappuse - E. Macii, D. Sciuto, and C. Silvano, "Asymptotic zerotransition activity encoding for address busses in low-power microprocessor-based systems," in Proceedings of the Great Lakes Symposium on VLSI, pp.
196. lappuse - S. Heo, K. Barr, M. Hampton, and K. Asanovic. Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines.
205. lappuse - N. Vijaykrishnan, M. Kandemir, MJ Irwin, HS Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using SimplePower.

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