CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 42.
68. lappuse
... variables and a random sample of functions with 5 to 18 variables . The minimal minterms were extracted using our FMM algorithm , and the prime cube covers were found using ESPRESSO [ 7 ] . Results show that minimal minterms are much ...
... variables and a random sample of functions with 5 to 18 variables . The minimal minterms were extracted using our FMM algorithm , and the prime cube covers were found using ESPRESSO [ 7 ] . Results show that minimal minterms are much ...
102. lappuse
... variables . The variables with indices 0 to 3 can be ac- cessed with one byte ( ldloc.0 1dloc.3 ) . Other variables require two ( 1dloc.s ) or four bytes ( 1dloc ) . It is straight- forward to allocate the most used values to the first ...
... variables . The variables with indices 0 to 3 can be ac- cessed with one byte ( ldloc.0 1dloc.3 ) . Other variables require two ( 1dloc.s ) or four bytes ( 1dloc ) . It is straight- forward to allocate the most used values to the first ...
276. lappuse
... variables by replacing them with Z. However , variables similar to XZS and XZE are still required to calculate the communication delay , and hence the throughput . To correctly relate these variables with Z , we must introduce ...
... variables by replacing them with Z. However , variables similar to XZS and XZE are still required to calculate the communication delay , and hence the throughput . To correctly relate these variables with Z , we must introduce ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx