CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 68.
25. lappuse
... units that implement op sorted by Unit Priorities ; 104 P - paths from FU.output to dst sorted by PathPriorities ; 05 106 07 08 09 10 11 12 13 14 15 16 17 18 calculate FU.timing.start ; if ( FU is not reserved in ss.res Table ) ...
... units that implement op sorted by Unit Priorities ; 104 P - paths from FU.output to dst sorted by PathPriorities ; 05 106 07 08 09 10 11 12 13 14 15 16 17 18 calculate FU.timing.start ; if ( FU is not reserved in ss.res Table ) ...
107. lappuse
... units can be made very fine , this method determines the upper bound on energy savings over any possible DVFS policy that can be applied for this program trace . Next , we will discuss the optimal or near - optimal V / f assign- ments ...
... units can be made very fine , this method determines the upper bound on energy savings over any possible DVFS policy that can be applied for this program trace . Next , we will discuss the optimal or near - optimal V / f assign- ments ...
108. lappuse
... units and computation - dominant scaling units can be identified in terms of the memory stall ratio . Note that IPC ( instruction per cycle ) or CPI ( cycle per instruc- tion ) cannot be used to distinguish memory - bound scaling units ...
... units and computation - dominant scaling units can be identified in terms of the memory stall ratio . Note that IPC ( instruction per cycle ) or CPI ( cycle per instruc- tion ) cannot be used to distinguish memory - bound scaling units ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx