CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 48.
143. lappuse
... transaction level simulation platform - and discusses the organization of transaction level models in systemC . Section 4 , presents the overall flow of our transaction level power modeling and estimation approach with an example ...
... transaction level simulation platform - and discusses the organization of transaction level models in systemC . Section 4 , presents the overall flow of our transaction level power modeling and estimation approach with an example ...
144. lappuse
... transaction level power characterization method to the set of tasks present in the current transaction level model . This is one of the unique features of the transaction level power modeling approach being explored in this work . Core ...
... transaction level power characterization method to the set of tasks present in the current transaction level model . This is one of the unique features of the transaction level power modeling approach being explored in this work . Core ...
145. lappuse
... transaction sequence is executing - and represent this entire sequence as a transaction then we can clearly see that the variation in power numbers can be quite high . This would correspond to a level 4 or even a higher node in the HTLP ...
... transaction sequence is executing - and represent this entire sequence as a transaction then we can clearly see that the variation in power numbers can be quite high . This would correspond to a level 4 or even a higher node in the HTLP ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx