CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 74.
40. lappuse
... tool called SPAM . This work tackles a similar problem to what we face but is targeted at single cache ASIPs with two identical banks whereas our tool targets highly configurable architectures that can have multiple caches of different ...
... tool called SPAM . This work tackles a similar problem to what we face but is targeted at single cache ASIPs with two identical banks whereas our tool targets highly configurable architectures that can have multiple caches of different ...
126. lappuse
... tool itself provides already major infrastructure components . As the basic architectural template of these approaches is fixed , the opportunities for architectural optimization are restricted . The other tool class mentioned gives ...
... tool itself provides already major infrastructure components . As the basic architectural template of these approaches is fixed , the opportunities for architectural optimization are restricted . The other tool class mentioned gives ...
289. lappuse
... tools . In order to obtain larger speedups , we have to modify the original C code to allow for the synthesis tool to determine aliases . Improved alias analysis could allow for data to be fetched by the FPGA much earlier and in some ...
... tools . In order to obtain larger speedups , we have to modify the original C code to allow for the synthesis tool to determine aliases . Improved alias analysis could allow for data to be fetched by the FPGA much earlier and in some ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx