CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 85.
138. lappuse
... tion and thereby process masks simultaneously . This model requires us to have multiple masks and copies of the frame ( for concurrent access ) available on the chip , e.g 3 PEs re- quire 3 frame copies present on chip . This increases ...
... tion and thereby process masks simultaneously . This model requires us to have multiple masks and copies of the frame ( for concurrent access ) available on the chip , e.g 3 PEs re- quire 3 frame copies present on chip . This increases ...
207. lappuse
... tion to exploit the potential of this architecture , the application must scale well to large node counts . Because the scientific goals of the project entail simulating very long time - scales , up to microseconds , strong scaling of a ...
... tion to exploit the potential of this architecture , the application must scale well to large node counts . Because the scientific goals of the project entail simulating very long time - scales , up to microseconds , strong scaling of a ...
246. lappuse
... tion . The XML file defines which methods are to be ex- ecuted in hardware and where the corresponding FPGA configurations reside . At class - invocation time , the class loader changes the Java bytecode of the application by re ...
... tion . The XML file defines which methods are to be ex- ecuted in hardware and where the corresponding FPGA configurations reside . At class - invocation time , the class loader changes the Java bytecode of the application by re ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx