CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 20.
1. lappuse
... threads . Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source ...
... threads . Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source ...
17. lappuse
... threads of control can inde- pendently be considered from other threads of control that are sep- arated by synchronization points . This is illustrated in Figure 3 : the control - flows of the concurrent blocks A and C are never ...
... threads of control can inde- pendently be considered from other threads of control that are sep- arated by synchronization points . This is illustrated in Figure 3 : the control - flows of the concurrent blocks A and C are never ...
246. lappuse
... Thread VMW Patched Java Bytecode Java Bridge Class TH JVM JNI HW Method Accelerator n Retrieve Parameters Wait Callback FPGA ... threads of the native im- plementation . The main thread that contains the " entry point " and controls the ...
... Thread VMW Patched Java Bytecode Java Bridge Class TH JVM JNI HW Method Accelerator n Retrieve Parameters Wait Callback FPGA ... threads of the native im- plementation . The main thread that contains the " entry point " and controls the ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx