CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 83.
191. lappuse
... techniques . offer no protection against vulnerabilities that are uninten- tionally built - into " trusted programs and exploited during execution . Recent techniques have extended the above ap- proaches to dynamically ensure code ...
... techniques . offer no protection against vulnerabilities that are uninten- tionally built - into " trusted programs and exploited during execution . Recent techniques have extended the above ap- proaches to dynamically ensure code ...
241. lappuse
... techniques ( JIT - CCS and IS - CS ) in interpretive simulation . 35 Base Simulator SAM SAM + IIF 30 25 S20 15 10 5 0 adpcm bluefish compress crc epic 9721 go 4 Figure 13- Performance of base simulator for ARM . 2 0 5 adpcm bluefish ...
... techniques ( JIT - CCS and IS - CS ) in interpretive simulation . 35 Base Simulator SAM SAM + IIF 30 25 S20 15 10 5 0 adpcm bluefish compress crc epic 9721 go 4 Figure 13- Performance of base simulator for ARM . 2 0 5 adpcm bluefish ...
242. lappuse
... techniques complement the recently proposed optimizations and further improve the performance ( up to 89 % ) of the simulator . Our techniques improved the performance ( up to 30 % ) of Simplescalar , a widely used interpretive ...
... techniques complement the recently proposed optimizations and further improve the performance ( up to 89 % ) of the simulator . Our techniques improved the performance ( up to 30 % ) of Simplescalar , a widely used interpretive ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx