CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 87.
82. lappuse
... technique in the context of NoCs and to propose an architecture for the switch inside the SDM router . This switch is the most critical component of an SDM - based NoC because its size is expected to increase . Indeed , in the extreme ...
... technique in the context of NoCs and to propose an architecture for the switch inside the SDM router . This switch is the most critical component of an SDM - based NoC because its size is expected to increase . Indeed , in the extreme ...
185. lappuse
... technique at the circuit level . The goal of this technique is to balance the power consumption at the gate level by using the sense amplifier based logic ( SABL ) implementation . SABL is a dynamic and differential logic style . The ...
... technique at the circuit level . The goal of this technique is to balance the power consumption at the gate level by using the sense amplifier based logic ( SABL ) implementation . SABL is a dynamic and differential logic style . The ...
220. lappuse
... technique for universal hash functions . This technique can yield savings in power consumption compa- rable to that of the parallel data paths technique but with significantly less area overhead . Instead of replicating the original ...
... technique for universal hash functions . This technique can yield savings in power consumption compa- rable to that of the parallel data paths technique but with significantly less area overhead . Instead of replicating the original ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx