CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 81.
20. lappuse
... synthesis tech- niques and the right bar shows the area consumption when using multiprocess synthesis . In summary , we achieved an area reduction up to 28.3 % constrained by a fixed latency . Alternatively , a speed- up factor of 2.75 ...
... synthesis tech- niques and the right bar shows the area consumption when using multiprocess synthesis . In summary , we achieved an area reduction up to 28.3 % constrained by a fixed latency . Alternatively , a speed- up factor of 2.75 ...
205. lappuse
... Synthesis of Digital Microfluidic Biochip Output : Resource binding Schedule Operation Resource 01 02 2x3 - array mixer 01 02 Storage unit ( 1 cell ) 2 03 2x4 - array mixer 04 Storage unit ( 1 cell ) 04 03 05 1x4 - array mixer 06 6 LED ...
... Synthesis of Digital Microfluidic Biochip Output : Resource binding Schedule Operation Resource 01 02 2x3 - array mixer 01 02 Storage unit ( 1 cell ) 2 03 2x4 - array mixer 04 Storage unit ( 1 cell ) 04 03 05 1x4 - array mixer 06 6 LED ...
244. lappuse
... synthesis ( producing FPGA configuration from bytecode ) to move any critical software section to reconfigurable hardware accelerators . Apart from the challenge of synthesising hardware at run- time ( runtime synthesis ) , the major ...
... synthesis ( producing FPGA configuration from bytecode ) to move any critical software section to reconfigurable hardware accelerators . Apart from the challenge of synthesising hardware at run- time ( runtime synthesis ) , the major ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx