CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 72.
60. lappuse
... structure ( see Figure 7 ) , which is used by the schedulers . Finally each task has a task specific data structure , which is dependent on the functionality of the task . The task specif- ic data structure contains ports and variables ...
... structure ( see Figure 7 ) , which is used by the schedulers . Finally each task has a task specific data structure , which is dependent on the functionality of the task . The task specif- ic data structure contains ports and variables ...
61. lappuse
... structures . When a connection is made , the port data structure is initialized with the base address of the channel buffer and the channel buffer size . The base address is different for differ- ent processors . The channel data structure ...
... structures . When a connection is made , the port data structure is initialized with the base address of the channel buffer and the channel buffer size . The base address is different for differ- ent processors . The channel data structure ...
144. lappuse
... structure ( HTLP - tree ) to organize the transaction level power characterization data . This structure is used by the SystemC power estimation module ( through the mapping / power model interface ) in conjunction with the transaction ...
... structure ( HTLP - tree ) to organize the transaction level power characterization data . This structure is used by the SystemC power estimation module ( through the mapping / power model interface ) in conjunction with the transaction ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx