CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 69.
39. lappuse
... solution that greatly simplifies the creation of targeted caches and automates the process of explicitly allocating individual memory access to caches and banks . The effectiveness of our solution is demonstrated with experimental ...
... solution that greatly simplifies the creation of targeted caches and automates the process of explicitly allocating individual memory access to caches and banks . The effectiveness of our solution is demonstrated with experimental ...
119. lappuse
... solution that is mostly used in the prior art . The first solution clearly comes with an overhead in the energy consumption of the system . The second solution has a negative im- pact on the execution time of the application which ...
... solution that is mostly used in the prior art . The first solution clearly comes with an overhead in the energy consumption of the system . The second solution has a negative im- pact on the execution time of the application which ...
120. lappuse
... solutions to demonstrate the concept . The first heuristic solution uses only the configuration parameter of the memories . It is a local greedy approach that looks at each task independently and if any of the memories of the given task ...
... solutions to demonstrate the concept . The first heuristic solution uses only the configuration parameter of the memories . It is a local greedy approach that looks at each task independently and if any of the memories of the given task ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx