CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 77.
4. lappuse
... single thread performance ( i.e. a single application running on a single microprocessor ) . This form of performance grew at an annual rate of ~ 60 % in the early- to mid - 1990's . In the mid - 1990's to early 2000's , the annual ...
... single thread performance ( i.e. a single application running on a single microprocessor ) . This form of performance grew at an annual rate of ~ 60 % in the early- to mid - 1990's . In the mid - 1990's to early 2000's , the annual ...
108. lappuse
... single V / f ? Yes meet deadline at a lower single V / ? No from memory - bound to CPU - dominant ? Yes Yes from CPU - dominant to memory - bound ? No scale up V / f Yes Figure 4 : The flowchart of the proposed runtime DVFS policy . 4 ...
... single V / f ? Yes meet deadline at a lower single V / ? No from memory - bound to CPU - dominant ? Yes Yes from CPU - dominant to memory - bound ? No scale up V / f Yes Figure 4 : The flowchart of the proposed runtime DVFS policy . 4 ...
176. lappuse
... single - input , single - output transformations . However , they are more com- plex compared to MixColumn Transformations comprising around 40 bitwise operations . Again , two Round Transfor- mations are unrolled within a loop ...
... single - input , single - output transformations . However , they are more com- plex compared to MixColumn Transformations comprising around 40 bitwise operations . Again , two Round Transfor- mations are unrolled within a loop ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx