CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 78.
237. lappuse
... simulation is the instruction and data memory access translation between host and target machines . The simulators must maintain and update the status of the simulated processor including memory and register values . A major challenge ...
... simulation is the instruction and data memory access translation between host and target machines . The simulators must maintain and update the status of the simulated processor including memory and register values . A major challenge ...
323. lappuse
... simulation sample . Before each interval is executed , we predict which phase the interval will belong to . To guide sampling , we keep track of which phase IDs already have a representative sample with a flag in the phase signature ...
... simulation sample . Before each interval is executed , we predict which phase the interval will belong to . To guide sampling , we keep track of which phase IDs already have a representative sample with a flag in the phase signature ...
324. lappuse
... Simulation Model . Simulation time ( seconds ) 100k 200k 400k 800k 1M 10M full 1000000 100000 10000 1000 100 10 1 bzip cjpeg djpeg gs gzip mpegenc mpeg average Figure 2 : Time in seconds comparing our cycle - close scheme with 25 ...
... Simulation Model . Simulation time ( seconds ) 100k 200k 400k 800k 1M 10M full 1000000 100000 10000 1000 100 10 1 bzip cjpeg djpeg gs gzip mpegenc mpeg average Figure 2 : Time in seconds comparing our cycle - close scheme with 25 ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx