CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 51.
221. lappuse
... signal mulsrc of multiplexers mux1 and mux2 are set to select lower in- put . This is then accumulated into register R4 using the adder / subtractor unit . The 2w - bit accumulated result at the end of the k + 1 clock cycles is stored ...
... signal mulsrc of multiplexers mux1 and mux2 are set to select lower in- put . This is then accumulated into register R4 using the adder / subtractor unit . The 2w - bit accumulated result at the end of the k + 1 clock cycles is stored ...
299. lappuse
... signal of the coprocessor wrapper . The remaining bits can be connected to additional coprocessors of the same architecture . The CODONE register set signal is con- nected to the done signal of the coprocessor . This register would be ...
... signal of the coprocessor wrapper . The remaining bits can be connected to additional coprocessors of the same architecture . The CODONE register set signal is con- nected to the done signal of the coprocessor . This register would be ...
304. lappuse
... signals simultaneously . As part of this processing each signal has to be filtered by a linear FIR . For instance , each signal could have been sampled from a dif- ferent channel , similar to a VoIP algorithm . Often , locality ...
... signals simultaneously . As part of this processing each signal has to be filtered by a linear FIR . For instance , each signal could have been sampled from a dif- ferent channel , similar to a VoIP algorithm . Often , locality ...
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