CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 80.
38. lappuse
... shows the baseline characteristics . The first row in the table contains the benchmark name . The first 6 applications are from the Mediabench set of benchmarks , while the seventh appli- cation is a widely used open source mp3 encoder ...
... shows the baseline characteristics . The first row in the table contains the benchmark name . The first 6 applications are from the Mediabench set of benchmarks , while the seventh appli- cation is a widely used open source mp3 encoder ...
109. lappuse
... shows that there is no need to use granularity smaller than 106 instructions . Figure 6 shows the energy consumption using the proposed DVFS policy for all benchmarks . Energy consumption is normalized to the energy consumption using ...
... shows that there is no need to use granularity smaller than 106 instructions . Figure 6 shows the energy consumption using the proposed DVFS policy for all benchmarks . Energy consumption is normalized to the energy consumption using ...
241. lappuse
... show the performance of Base Simulator for ARM and Sparc processor models respectively . In these figures , the first bar shows the performance of Base Simulator that that implements the JIT - CCS and IS - CS optimizations . The second ...
... show the performance of Base Simulator for ARM and Sparc processor models respectively . In these figures , the first bar shows the performance of Base Simulator that that implements the JIT - CCS and IS - CS optimizations . The second ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx