CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 83.
59. lappuse
... shown . Group 3 consists of functions to start , pause , continue , and stop tasks . They all take the task as input . The functions in group 4 are used in the mainMethod of the tasks . The reconfiguration - aware tasks use the four ...
... shown . Group 3 consists of functions to start , pause , continue , and stop tasks . They all take the task as input . The functions in group 4 are used in the mainMethod of the tasks . The reconfiguration - aware tasks use the four ...
222. lappuse
... shown in Figure 1 is de- termined by the multiplier . Overall , the dynamic power consumption of a w - bit LCH data path decreases as : O ( w1 ) if the critical path delays remain unchanged , so using small size data paths can reduce ...
... shown in Figure 1 is de- termined by the multiplier . Overall , the dynamic power consumption of a w - bit LCH data path decreases as : O ( w1 ) if the critical path delays remain unchanged , so using small size data paths can reduce ...
310. lappuse
... shown in a two - dimensional DFG ( 2DFG ) . An example is shown in Figure 1 . = = V to integers . For a node u Є V , the value of r ( u ) is the number of delays drawn from each of its incoming edges of node u and pushed to all of its ...
... shown in a two - dimensional DFG ( 2DFG ) . An example is shown in Figure 1 . = = V to integers . For a node u Є V , the value of r ( u ) is the number of delays drawn from each of its incoming edges of node u and pushed to all of its ...
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Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx