CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 67.
41. lappuse
... selection process towards an optimal solution . 3.1 Allocation Algorithm The aim of the allocation algorithm is to assign grouped memory access instructions to appropriately sized banks to minimize cache misses , and minimize ...
... selection process towards an optimal solution . 3.1 Allocation Algorithm The aim of the allocation algorithm is to assign grouped memory access instructions to appropriately sized banks to minimize cache misses , and minimize ...
77. lappuse
... selection problem as a pure path selection problem . Given an interconnection network Io and an application graph A , we must select a path π for every flow ƒ € F such that bandwidth ( 1 ) and latency ( 2 ) requirements of the flow are ...
... selection problem as a pure path selection problem . Given an interconnection network Io and an application graph A , we must select a path π for every flow ƒ € F such that bandwidth ( 1 ) and latency ( 2 ) requirements of the flow are ...
170. lappuse
Algorithm 2 : Improved Custom Instruction Selection Heuristic selectPatterns ( in ) Input : in : partial selection of patterns , instances , and cor- responding wcet Output : complete selection of patterns , instances , and cor ...
Algorithm 2 : Improved Custom Instruction Selection Heuristic selectPatterns ( in ) Input : in : partial selection of patterns , instances , and cor- responding wcet Output : complete selection of patterns , instances , and cor ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx