CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 38.
111. lappuse
... scheme over previously published DVS schemes is its ability to provide hard QoS guarantees while still achieving considerable energy savings . Our scheme can handle workloads characterized by both , the data- dependent variability in ...
... scheme over previously published DVS schemes is its ability to provide hard QoS guarantees while still achieving considerable energy savings . Our scheme can handle workloads characterized by both , the data- dependent variability in ...
116. lappuse
... scheme is denoted as DVS and DVS iDPM . ing on and off of PE2 was assumed to occur in zero time under the control of an ideal ( " oracle " ) DPM . Although unrealistic , such a configuration is useful for the analysis because it ...
... scheme is denoted as DVS and DVS iDPM . ing on and off of PE2 was assumed to occur in zero time under the control of an ideal ( " oracle " ) DPM . Although unrealistic , such a configuration is useful for the analysis because it ...
216. lappuse
... scheme adopted at the specific level , i.e. , level i . The KOA scheme is applied at the ith level if m = 1 , or the BC with k multiplication units is used if m1 = k > 1 . After hierarchically decomposed , the hybrid multipliers need a ...
... scheme adopted at the specific level , i.e. , level i . The KOA scheme is applied at the ith level if m = 1 , or the BC with k multiplication units is used if m1 = k > 1 . After hierarchically decomposed , the hybrid multipliers need a ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx