CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 66.
19. lappuse
... SCHEDULING AND BINDING This section shows , how the concurrency graph can be used as an essential data structure for multiprocess scheduling . The goal is not to propose new scheduling algorithms , but to present the needed extensions ...
... SCHEDULING AND BINDING This section shows , how the concurrency graph can be used as an essential data structure for multiprocess scheduling . The goal is not to propose new scheduling algorithms , but to present the needed extensions ...
22. lappuse
... scheduling and binding algorithms in the area of high level synthesis , retargetable compilers . Force directed scheduling ( FDS ) [ 1 ] , [ 2 ] is commonly used to solve the timed constrained scheduling problem . This algorithm ...
... scheduling and binding algorithms in the area of high level synthesis , retargetable compilers . Force directed scheduling ( FDS ) [ 1 ] , [ 2 ] is commonly used to solve the timed constrained scheduling problem . This algorithm ...
73. lappuse
... scheduling problem is a traditional topic in computer science , most previous work neglects the inter- processor ... scheduling problem remains an important problem for NoC design . 5.1.2 Problem Formulation A simple but important ...
... scheduling problem is a traditional topic in computer science , most previous work neglects the inter- processor ... scheduling problem remains an important problem for NoC design . 5.1.2 Problem Formulation A simple but important ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx