CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 26.
105. lappuse
... scaling ( DVFS ) , a technique to vary voltage / frequency on the fly , has emerged as a powerful and practical power / energy reduction technique that exploits computation slack due to relaxed deadlines and memory accesses . DVFS has ...
... scaling ( DVFS ) , a technique to vary voltage / frequency on the fly , has emerged as a powerful and practical power / energy reduction technique that exploits computation slack due to relaxed deadlines and memory accesses . DVFS has ...
107. lappuse
... scaling units can be made very fine , this method determines the upper bound on energy savings over any possible DVFS policy that can be ... scaling units . scaling point ( instruction counter interrupt ) deadline1 deadline2 deadline3 107.
... scaling units can be made very fine , this method determines the upper bound on energy savings over any possible DVFS policy that can be ... scaling units . scaling point ( instruction counter interrupt ) deadline1 deadline2 deadline3 107.
108. lappuse
... scaling points and scal- ing criteria . We will assume the scaling points are fixed and focus on the scaling criteria in this section . Based on the previous discussion , the DVFS policy should be able to identify computation - dominant ...
... scaling points and scal- ing criteria . We will assume the scaling points are fixed and focus on the scaling criteria in this section . Based on the previous discussion , the DVFS policy should be able to identify computation - dominant ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx