CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 77.
16. lappuse
... resource sharing using a dynamic programming approach has been presented by Chang and Pedram [ 5 ] . But this approach is limited to data - independent con- trol structures and resource sharing is restricted to mutually exclu- sive ...
... resource sharing using a dynamic programming approach has been presented by Chang and Pedram [ 5 ] . But this approach is limited to data - independent con- trol structures and resource sharing is restricted to mutually exclu- sive ...
30. lappuse
... resource needs of each c - step , the edges all have equal weight . Therefore by convention , the same number c - steps are matched across DFGs . has are S so DFC resou Then I oret esourc. maximum tolerable latency ( or optionally , the ...
... resource needs of each c - step , the edges all have equal weight . Therefore by convention , the same number c - steps are matched across DFGs . has are S so DFC resou Then I oret esourc. maximum tolerable latency ( or optionally , the ...
216. lappuse
... resource efficiency of the built - in hardware multipliers in many Xilinx Virtex - II® chips . The Xilinx Vertex - II FPGA comes with embedded ... resources must combine the performance advantages of parallel multipliers and the resource 216.
... resource efficiency of the built - in hardware multipliers in many Xilinx Virtex - II® chips . The Xilinx Vertex - II FPGA comes with embedded ... resources must combine the performance advantages of parallel multipliers and the resource 216.
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx