CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 35.
96. lappuse
... requests Get page addr and size from mapping table Read Request page N Write Yes No Yes No N = 0 N = 0 Copy the compressed page to compressed buffer Yes No Write page 0 to addr used = 1 Free old page N Decompress to clean buffer Read ...
... requests Get page addr and size from mapping table Read Request page N Write Yes No Yes No N = 0 N = 0 Copy the compressed page to compressed buffer Yes No Write page 0 to addr used = 1 Free old page N Decompress to clean buffer Read ...
97. lappuse
... request buffer Request Handling Replace old block 7 with new block 7 Figure 5 : Linear , fixed - size blocks in RAM disk Tbl Compressed Chunk 1 Chunk 2 Chunk 3 Chunk4 Block 0 254 byte Block 0 254 byte Block 7 286 byte Block 0 Block 7 ...
... request buffer Request Handling Replace old block 7 with new block 7 Figure 5 : Linear , fixed - size blocks in RAM disk Tbl Compressed Chunk 1 Chunk 2 Chunk 3 Chunk4 Block 0 254 byte Block 0 254 byte Block 7 286 byte Block 0 Block 7 ...
158. lappuse
... requests in the request buffer . The prefetch engine monitors the re- quest buffer , and it does not let the request buffer be empty . If the request buffer is always full , the activity on the data bus remains uninterrupted . This ...
... requests in the request buffer . The prefetch engine monitors the re- quest buffer , and it does not let the request buffer be empty . If the request buffer is always full , the activity on the data bus remains uninterrupted . This ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx